use group hold before streaming will make register effect delay one
frmae
Change-Id: Ia28b9981d38e3fe5132a62da277495e61c7dd052
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
1.It will be added by remap_pfn_range_internal;
2.Fix compile warning:
drivers/misc/rockchip/pcie-rkep.c:613:23: error: assignment of read-only member 'vm_flags'
613 | vma->vm_flags |= VM_IO;
| ^~
drivers/misc/rockchip/pcie-rkep.c:614:23: error: assignment of read-only member 'vm_flags'
614 | vma->vm_flags |= (VM_DONTEXPAND | VM_DONTDUMP);
| ^~
Change-Id: I3c705248b216c246a8efb25f28c44fc419110fee
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Since the PSR feature can help to reduce the power consumption, the
Source device, which can support PSR function, should enable PSR if
the PSR capability of Sink device is detected rather than depending
on the user to add 'support-psr' DTS property manually.
Change-Id: I2f51312621f62519f388e06561fb61f01145256b
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Before this commit, the drm_self_refresh_helper_init() was called
in &component_ops.bind() of VOP/VOP2 drivers. The VOP or VPs,
which do not want to enable PSR functionality, will also initialize
the self refresh helper.
Since it wastes resources(e.g., allocating &drm_self_refresh_data and
initializing &drm_self_refresh_data.entry_work), we move the init and
cleanup process from bind()/unbind() of VOP/VOP2 drivers to the ones
of eDP/RGB drivers, which can support PSR functionality.
Change-Id: Ie7643b54f42ea3d5ab7b0cdbc77ccfdb06c614b9
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
If no errno assignment for this case, there will be a warning:
drivers/gpu/drm/rockchip/rockchip_drm_vop.c:5754 vop_create_crtc() warn:
missing error code 'ret'
Change-Id: I9e78fe99b3ca24d8734ee286b1dc1f0908721f25
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
First of all, since the PSR feature can help to reduce the power
consumption, the Source device, which can support PSR function,
should enable PSR if the PSR capability of Sink device is detected
rather than depending on the user to add 'support-psr' DTS property
manually.
Different platforms that use the same Analogix DP bridge driver may
have different methods for parsing the PSR capability. Therefore, add
a new flag &analogix_dp_plat_data.disable_psr to disable PSR forcely,
which set in the platform side, should be more reasonable.
If the user truly does not want to enable PSR function or the Panel
has something wrong with it, the property 'rockchip,disable-psr' will
be helpful.
Fixes: 9622f2d0f1 ("drm/bridge: analogix_dp: disable PSR feature by default")
Change-Id: Id2fce34857df80de5a1ec97f342709a6e2840ed4
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
drivers/pci/controller/dwc/pcie-dw-dmatest.c:157:5: error: no previous prototype for 'rk_pcie_local_dma_tobus_block' [-Werror=missing-prototypes]
Change-Id: I616a4759d856a72b469996a3c6f07e4af90d5616
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Since the PSR feature can help to reduce the power consumption, the
Source device, which can support PSR function, should enable PSR if
the PSR capability of Sink device is detected.
If the user truly does not want to enable PSR function or the Panel
has something wrong with it, the property 'rockchip,disable-psr' will
be helpful.
Change-Id: I03b3c83c7c88ea3fc3ccd447e5c5da49e16f22a9
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
After converting analogix_dp.txt to yaml, the descriptions of
properties for dual-channel and split modes, which have been
already supported, should be added synchronously.
Change-Id: I8a66ef3ed8c469eca0c9d6e06a827c1f1a8d58a1
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The RK3568 eDP TX controller is almost the same as that of RK3399.
It supports RBR/HBR with 1/2/4 lanes and the max supported resolution
is 2560x1600p60.
The slight difference with RK3399 is the newly added 'apb' reset,
which is just like that of RK3588/RK3576.
Change-Id: Ifd5bc2d8f337b794a6d2983b689d2bd2271d78c2
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The RK3576 eDP TX controller is the same as that of RK3588.
Change-Id: I3f32329866bc70f6f26132eb583f520e39f53594
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Compared with RK3288/RK3399, the HBR2 link rate support is the main
improvement of RK3588 eDP TX controller, and there are also two
independent eDP display interfaces on RK3588 Soc.
The newly added 'apb' reset is to ensure the APB bus of eDP controller
works well on the RK3588 SoC.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Change-Id: If3864613762898624ba39ad0395516a4ebb02732
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Link: https://lore.kernel.org/r/20250310104114.2608063-10-damon.ding@rock-chips.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
(cherry picked from commit f855146263b14abadd8d5bd0e280e54fbab3bd18)
If the DSC mode with a compression rate lower than 0.375 is to
be supported, the dclk clock source of the VOP bound to HDMI must
be a CRU PLL that supports fractional frequency division.
However, in most scenarios, HDMI is unable to be assigned such a
PLL. So in this scenario, instead of enabling DSC, we switch to
YUV420 format.
Change-Id: I450cdd5857e4384894651ed063fac152a8d9bb0f
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Only searches rockchip,pvtpll-table when bin-specific property is absent.
Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Change-Id: Ic728e39851cdd8c32970d81249cf295a3b8d6aeb
Avoid auto_gating/int_mask register state loss after reset
Change-Id: Ie341f0f58f398476daacffdd90565d39c68faa54
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
1. Resetting only core_clk will cause abnormal src1 status in blend
scenarios, so both aclk and core_clk must be reset.
2. Avoid the issue by shielding the wrong interrupt.
Fixes: a2a7ce0bf0 ("video: rockchip: rga3: add fix for hardware issuewith RK3576")
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I3cb0034f6c3090faca19cea2c2f5b375388271f8
