Split the driver code into separate source file
Fixes: 0ca8d654bd ("drm/bridge: Add support for BU18TL82-M/BU18RL82-M")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Id46cfbab9b21812432da0db1cfb4306feb79c595
The work ata_scsi_dev_rescan will hangup and can not wakeup if PM
enter sleep at the sata device wake-up process.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I44045505c2e691102ab90ba3b2ae3031e7bab0a6
reserved sram memory from 0xff6ff000 to 0xff6fffff for
mcu wrap
Signed-off-by: aaron.sun <aaron.sun@rock-chips.com>
Change-Id: I116476a5d787014088788191acf2cef7f1c921c4
When the display mode support yuv420, It can get the min bpp
12. If the display mode only support yuv420 and downstream
device don't set VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED
bit in DPCD, filtering this mode.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I1ba05ce8ad622ba6a25b48025fe2a3efeaa289a1
Enable CONFIG_HARDLOCKUP_DETECTOR_OTHER_CPU which enable
CONFIG_SOFTLOCKUP_DETECTOR too.
The kernel can detect the lockup that cpu stuck with interrupts disabled.
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: I34b3f1c99bc99c52c91b84c26c45e01207e60739
Emulate NMIs on systems where they are not available by using timer
interrupts on other cpus. Each cpu will use its softlockup hrtimer
to check that the next cpu is processing hrtimer interrupts by
verifying that a counter is increasing.
This patch is useful on systems where the hardlockup detector is not
available due to a lack of NMIs, for example most ARM SoCs.
Without this patch any cpu stuck with interrupts disabled can
cause a hardware watchdog reset with no debugging information,
but with this patch the kernel can detect the lockup and panic,
which can result in useful debugging info.
Change-Id: Ia5faf50243e19c1755201212e04c8892d929785a
Signed-off-by: Colin Cross <ccross@android.com>
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
On RK3588 platform, the USB Host port may miss disconnect
falling edge irq which is used to detect usb device plug in.
This always happens in the following two cases:
1. For RK3588 ARM PC, boot system from U Disk which connected
the USB2 Host port (EHCI & OHCI Controller);
2. For RK3588 EVB, increase the disconnect filer counter to
0xF4240 in the reg USB2PHY_GRF_DIS_CON. That is, the
disconnect rising/falling irq filter time is set to 10ms
depend on the 100MHz pclk.
In this case, we can clear the host_disconnect state depend
on the linestate irq which also means that an usb device is
connecting to the port.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Iadde3278c3383c0d477a0b9998871a5a1f5fe206
Clean up power up/off handing for acodec, make the DAC
PSRR feature is better ~14.5dB.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Change-Id: Ia735d2f5e2134c86d35656fb027352a45093d9a5
csm->cgc->cproc->ie, and sharp no support
limit range from csm, so fix csm range to full and
cgc to config limit or full range.
Change-Id: Iccc3e7254d55c0e7b61e33028af88e7685e9f1e5
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
When enable cpu auto power down, reading pcsr causes "synchronous
external abort" when cpu is power down. Disable the SError during
reading pcsr, and skip reading pcsr if cpu is power down.
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: Id02b998f621daf440a602faf10439612868d731f
Generally, the set the rk_dma_heap_cma as an environment variable that
was passed to kernel via bootargs. Due to thuner-boot, we fixed the
bootargs in DTS.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: I725fa3cde59c8b1e6c84fecbc0d1611d333b69e3
BU18TL82-M supports MIPI DSI and LVDS data
transmission by ROHM's original CDR (Clock Data
Recovery) technology. This chip is the serial interface
transmitter IC of the Clockless Link-BD series.
BU18TL82-M converts the MIPI DSI and LVDS data
stream into Clockless Link format transmit through 2
pairs of differential wires.
BU18RL82-M supports LVDS data transmission by
ROHM's original CDR (Clock Data Recovery) technology.
This chip is serial interface receiver IC of the Clockless
Link-BD series.
BU18RL82-M converts Clockless link stream into a
LVDS format, and transmits through one or two ports of
LVDS.
Flexible Input / Output mode is suitable for a variety of
application interface.
Change-Id: Ia8693b84d910ce9e08c49b9957bd5682b8625b0f
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
when the hdisplay more than 4096, vop need use splice mode to
output image. So another vop port need config in load protect
function.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I64b7726397553af4aeb3cf35ef751b73345497ad
In order to get the hdisplay of the display mode, attaching the
crtc to drm state.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I85909a414767b0bdd078edfa0a17df97b7612538
1. ABA -> ABB.
2. The output has an offset and is placed in win0 for processing.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: Id501ad32fc887b6e88dfaec5cfdb1842169951bd
Use the DPCD Automated Testing Filed to auto test DP SI.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Ic3c01cd2068125ff415a205e57a0b873cc2541fc
For linestate irq as a wakeup source, we need to reconfigure the
linestate filter value base on 32KHz clk at suspend time, and restore
it to the default when the system resume.
By the way, set the grf to handle the phy status when the system
suspend, which can support the linestate wakeup even the PD of the
USB controller was off for RK3588 OTG1 port.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I630855981082298d079d9c713029a7e3093b09cd
Add a child node 'peak' to stat the peak size for dmabuf.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I6ee9e69f60e9c7660477dafb3d7f789677406abb
The system memory presure always take care of the peak memory size, for
dmabuf, the peak size is useful when media module to design drivers.
Get peak can show the peak size currently, and reset peak can clear it.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I56b0323167361e11dd657a22449aad65751fc81a
This patch add uevent to notify the application layer how much ppm
is different between USB clk and AUDIO clk.
The event include two parts USB_STATE and PPM. For example:
g_audio_work: sent uac uevent USB_STATE=SET_AUDIO_CLK PPM=12
g_audio_work: sent uac uevent USB_STATE=SET_AUDIO_CLK PPM=-1
Note: The ppm compensation depends on the method implement of
clk drift and compensation in the audio driver (eg. sound/soc/
rockchip/rockchip_i2s.c). So if you want the ppm compensation to
take effect, please make sure the related driver has implemented.
Change-Id: I71cb431cf4798028e1b62c1570eb5911b17b3ddc
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
When the request pixelclk is under 600MHz, vop2 will
calculate dclk first. When the dsc is enabled. vop2 will
calculate dsc clk first then dclk. the dclk rate get from
the first time calclulate dsc clk and second set dck may
be different, which will get wrong dsc clk when use the
latest dclk rate to recalculate it. So the dclk should
be calculated before dsc clk when dsc enable and pixelclk
is under 600MHz.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: If6794a266dd624be2cd14ab1be0ee0c0db20b49a
