1. Change length according to speed grade.
2. Set supported platforms according to SoC version and speed grade.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I448d3f784216bc034ea2900e5ab837920721cdd0
This patch fixes the following compile warning:
drivers/phy/rockchip/phy-rockchip-inno-usb2.c:1225:3: warning: Value stored to 'sch_work' is never read
drivers/phy/rockchip/phy-rockchip-inno-usb2.c:1235:4: warning: Value stored to 'sch_work' is never read
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I053f5775b28707a45530405084e3df827edde882
The system calls pm_runtime_get_noresume() to prevent device
from entering to runtime suspend status when reboot, and the
pm_runtime_put_sync_suspend() is called in a delay work,
so when reboot the power domain may be power on,
but the regulator is disabled, it's not allowed.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ie25451ddf4fc866e93e7272a8d9a809919a96e1d
When system resume, all power domains will power on in
dpm_noirq_resume_devices(), if vdd gpu is disabled before system
suspend, the pd gpu will failed to power on when system resume,
the detail as follows:
rockchip-pm-domain fd8d8000.power-management:power-controller: failed to get ack on domain 'gpu', target_idle = 0, target_ack = 0, val=0x8080f
Kernel panic - not syncing: panic_on_set_idle set ...
CPU: 0 PID: 1947 Comm: Binder:352_2 Not tainted 5.10.66 #960
Hardware name: Rockchip RK3588 EVB1 LP4 V10 Board (DT)
Call trace:
dump_backtrace+0x0/0x1c8
show_stack+0x1c/0x2c
dump_stack_lvl+0xdc/0x12c
dump_stack+0x1c/0x64
panic+0x150/0x3a4
rockchip_pmu_set_idle_request+0x1f8/0x1fc
rockchip_pd_power+0x11c/0x1e0
rockchip_pd_power_on+0x28/0x38
genpd_sync_power_on+0xf4/0x134
genpd_resume_noirq+0x70/0xd0
device_resume_noirq+0x1a8/0x410
dpm_noirq_resume_devices+0x100/0x55c
dpm_resume_noirq+0x18/0x34
suspend_enter+0x33c/0x52c
suspend_devices_and_enter+0xec/0x338
enter_state+0x12c/0x3f8
pm_suspend+0x60/0xcc
state_store+0x108/0x148
kobj_attr_store+0x1c/0x34
sysfs_kf_write+0x40/0x58
kernfs_fop_write_iter+0xf0/0x194
vfs_write+0x328/0x390
ksys_write+0x78/0xe8
__arm64_sys_write+0x20/0x30
el0_svc_common+0xc0/0x23c
do_el0_svc+0x28/0x88
el0_svc+0x14/0x24
el0_sync_handler+0x88/0xec
el0_sync+0x1a8/0x1c0
SMP: stopping secondary CPUs
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I89f80d37ab2cc61c715bce3f8a25c26552918922
Split the driver code into separate source file
Fixes: 0ca8d654bd ("drm/bridge: Add support for BU18TL82-M/BU18RL82-M")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Id46cfbab9b21812432da0db1cfb4306feb79c595
The work ata_scsi_dev_rescan will hangup and can not wakeup if PM
enter sleep at the sata device wake-up process.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I44045505c2e691102ab90ba3b2ae3031e7bab0a6
reserved sram memory from 0xff6ff000 to 0xff6fffff for
mcu wrap
Signed-off-by: aaron.sun <aaron.sun@rock-chips.com>
Change-Id: I116476a5d787014088788191acf2cef7f1c921c4
When the display mode support yuv420, It can get the min bpp
12. If the display mode only support yuv420 and downstream
device don't set VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED
bit in DPCD, filtering this mode.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I1ba05ce8ad622ba6a25b48025fe2a3efeaa289a1
Enable CONFIG_HARDLOCKUP_DETECTOR_OTHER_CPU which enable
CONFIG_SOFTLOCKUP_DETECTOR too.
The kernel can detect the lockup that cpu stuck with interrupts disabled.
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: I34b3f1c99bc99c52c91b84c26c45e01207e60739
Emulate NMIs on systems where they are not available by using timer
interrupts on other cpus. Each cpu will use its softlockup hrtimer
to check that the next cpu is processing hrtimer interrupts by
verifying that a counter is increasing.
This patch is useful on systems where the hardlockup detector is not
available due to a lack of NMIs, for example most ARM SoCs.
Without this patch any cpu stuck with interrupts disabled can
cause a hardware watchdog reset with no debugging information,
but with this patch the kernel can detect the lockup and panic,
which can result in useful debugging info.
Change-Id: Ia5faf50243e19c1755201212e04c8892d929785a
Signed-off-by: Colin Cross <ccross@android.com>
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
On RK3588 platform, the USB Host port may miss disconnect
falling edge irq which is used to detect usb device plug in.
This always happens in the following two cases:
1. For RK3588 ARM PC, boot system from U Disk which connected
the USB2 Host port (EHCI & OHCI Controller);
2. For RK3588 EVB, increase the disconnect filer counter to
0xF4240 in the reg USB2PHY_GRF_DIS_CON. That is, the
disconnect rising/falling irq filter time is set to 10ms
depend on the 100MHz pclk.
In this case, we can clear the host_disconnect state depend
on the linestate irq which also means that an usb device is
connecting to the port.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Iadde3278c3383c0d477a0b9998871a5a1f5fe206
Clean up power up/off handing for acodec, make the DAC
PSRR feature is better ~14.5dB.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Change-Id: Ia735d2f5e2134c86d35656fb027352a45093d9a5
csm->cgc->cproc->ie, and sharp no support
limit range from csm, so fix csm range to full and
cgc to config limit or full range.
Change-Id: Iccc3e7254d55c0e7b61e33028af88e7685e9f1e5
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
When enable cpu auto power down, reading pcsr causes "synchronous
external abort" when cpu is power down. Disable the SError during
reading pcsr, and skip reading pcsr if cpu is power down.
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: Id02b998f621daf440a602faf10439612868d731f
Generally, the set the rk_dma_heap_cma as an environment variable that
was passed to kernel via bootargs. Due to thuner-boot, we fixed the
bootargs in DTS.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: I725fa3cde59c8b1e6c84fecbc0d1611d333b69e3
BU18TL82-M supports MIPI DSI and LVDS data
transmission by ROHM's original CDR (Clock Data
Recovery) technology. This chip is the serial interface
transmitter IC of the Clockless Link-BD series.
BU18TL82-M converts the MIPI DSI and LVDS data
stream into Clockless Link format transmit through 2
pairs of differential wires.
BU18RL82-M supports LVDS data transmission by
ROHM's original CDR (Clock Data Recovery) technology.
This chip is serial interface receiver IC of the Clockless
Link-BD series.
BU18RL82-M converts Clockless link stream into a
LVDS format, and transmits through one or two ports of
LVDS.
Flexible Input / Output mode is suitable for a variety of
application interface.
Change-Id: Ia8693b84d910ce9e08c49b9957bd5682b8625b0f
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
when the hdisplay more than 4096, vop need use splice mode to
output image. So another vop port need config in load protect
function.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I64b7726397553af4aeb3cf35ef751b73345497ad
In order to get the hdisplay of the display mode, attaching the
crtc to drm state.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I85909a414767b0bdd078edfa0a17df97b7612538
1. ABA -> ABB.
2. The output has an offset and is placed in win0 for processing.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: Id501ad32fc887b6e88dfaec5cfdb1842169951bd
Use the DPCD Automated Testing Filed to auto test DP SI.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Ic3c01cd2068125ff415a205e57a0b873cc2541fc
