According to commit 9bde4e671f ("drm/rockchip: vop: fix iommu crash
with async atomic")
These two callback were added to avoid iommu crash on async
commit caused by drm_atomic_clean_old_fb after drm_atomic_async_commit.
drm_atomic_clean_old_fb was removed after commit
e00fb8564e ("drm: Stop updating plane->crtc/fb/old_fb on atomic drivers")
So we can remove them to make life simpler.
Change-Id: Iea1f2dbadd9bcfad5b8447831c0d31068d4fa97b
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
We assign window between vp by plane_mask now, no
need to check which vp is activated from register.
Change-Id: I89d22f253dcd26898dc79304d51b8a8d9e802bb2
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
According to macronix website, there is no mx66l51235l part number.
The chip detected as such is actually mx66l51235f. Rename the flash.
Do not update the mx66l51235l name from the spi_nor_dev_ids[], since
there are dt that are using this compatible.
Change-Id: I23594ca8301572df8024b413379e1d688f8ca793
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit d406f49b05)
Add support for w25q512jvq. This is of the same series chip with
w25q256jv, which is already supported, but with size doubled and
different JEDEC ID.
Tested on Intel whitley platform with dd from/to the flash for
read/write respectly, and flash_erase for erasing the flash.
Change-Id: I3b4243a0391ae994af131062a8a21f659494fccb
Signed-off-by: Shuhao Mai <shuhao.mai.1990@gmail.com>
[ta: put flash_info flags in order, first SPI_NOR_DUAL_READ, then
SPI_NOR_QUAD_READ]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20210208075303.4200-1-shuhao.mai.1990@gmail.com
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit ff013330fb)
The relevant changes to the already existing GD5F1GQ4UExxG support has
been determined by consulting the GigaDevice product change notice
AN-0392-10, version 1.0 from November 30, 2020.
As the overlaps are huge, variable names have been generalized
accordingly.
Apart from the lowered ECC strength (4 instead of 8 bits per 512 bytes),
the new device ID, and the extra quad IO dummy byte, no changes had to
be taken into account.
New hardware features are not supported, namely:
- Power on reset
- Unique ID
- Double transfer rate (DTR)
- Parameter page
- Random data quad IO
The inverted semantic of the "driver strength" register bits, defaulting
to 100% instead of 50% for the Q5 devices, got ignored as the driver has
never touched them anyway.
The no longer supported "read from cache during block erase"
functionality is not reflected as the current SPI NAND core does not
support it anyway.
Implementation has been tested on MediaTek MT7688 based GARDENA smart
Gateways using both, GigaDevice GD5F1GQ5UEYIG and GD5F1GQ4UBYIG.
Change-Id: I0e819a07711e58542af2bcf753b4ecb10eb9f882
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20210211113619.3502-1-code@reto-schneider.ch
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 469b992489)
The Macronix MX35LF1G24AD(/2G24AD/4G24AD) are 3V, 1G/2G/4Gbit serial
SLC NAND flash device (without on-die ECC).
Validated by read, erase, read back, write, read back on Xilinx Zynq
PicoZed FPGA board which included Macronix SPI Host(drivers/spi/spi-mxic.c)
& S/W BCH ecc(drivers/mtd/nand/ecc-sw-bch.c) with bug fixing patch
(mtd: nand: ecc-bch: Fix the size of calc_buf/code_buf of the BCH).
Change-Id: I88c68306bdc61a856cef9e5af1bc4c1e19fc2abd
Signed-off-by: YouChing Lin <ycllin@mxic.com.tw>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/1607570529-22341-3-git-send-email-ycllin@mxic.com.tw
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit ee4e0eafa4)
pm_runtime_force_suspend/pm_runtime_force_resume will not work
if the device is in suspend when pm_runtime is disabled.
Change-Id: I7179ecab2b059b43fab6d84683e52ae5c21096ae
Signed-off-by: Liang Chen <cl@rock-chips.com>
Using BBT in flash to avoid frequently flash operation for bbt info.
And it's secure to record the bad block info in bbt instead of
programing to the bad block with extremely unstable performance directly.
Change-Id: Icfe816c2c17ff3b747ce0a2512b1d9d6d0129fa0
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
1.cherry-pick from kernel-4.19
2.fix compile errors and adapt to kernel-5.10
Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com>
Change-Id: I5dc11d3c8a2559303d96b3206fafadb46f95ed0f
Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>
DPTX implements the programmable SSC down-spreading with up to
0.5% modulation amplitude and 30k/33k modulation frequency.
Change-Id: I2c3eae8f27c84eb1b22eac8973691e0276c1588e
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
No need to use CONFIG_MALI_BIFROST_FOR_LINUX
after px30/rk3326 Android and Linux device
use the same bifrost_device_driver "drivers/gpu/arm/bifrost".
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
Change-Id: Ia4c9c79be2c10d5d708a8ea1bb4bc5d49c97267b
Because they are no longer useful,
after rk3288/rk3399 Android and Linux device
use the same midgard_device_driver "drivers/gpu/arm/midgard".
Change-Id: I7ccc3c99fdfdde5a0ea12a7f3e1931fd5f1ce4cb
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
RK3568 USB DWC3 controllers require to disable receiver detection
in P3 for correct detection of USB devices. And this quirk to set
the GUSB3PIPECTL.DISRXDETINP3, then the DWC3 core will change the
PHY power state to P2 and then perform receiver detection. After
receiver detection, the DWC3 core will change the PHY power state
to P3 state.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Iaad3f7ce2c4dee1788539781e3bcfbb39458f5d6
According to the programming guide, it needs to reset the
device with DCTL.CSftRst when switching from host to device.
The current code use dwc3_core_soft_reset() to do DCTL.CSftRst,
it will also duplicate phy init which has been done in runtime
resume routine, this cause the phy init/exit operations are
unbalanced.
Without this patch, the dwc3 gadget resume fail on RK3568 EVB1
with the following log:
dwc3 fcc00000.dwc3: failed to enable ep0out
It's because that the init_count of usb3 phy is not 0 when
resume, so the dwc3 fail to call usb3 phy init, and the 3.0
pipe clock is not be running.
Fixes: b48bcb27ae ("FROMGIT: usb: dwc3: core: Do core softreset when switch mode")
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I58ec26f9f007c94f8979eeeb9a9d683c6db9548f
Some linux app(cusor) may set negative coordinates(crtc_x/y)
And some linux app(mpv) may set coordinates outside the screen.
These are both unsupported on rockchip vop.
so we use clipped coordinates here.
Change-Id: I63288cf9120cea75e784d49bc88b591f243e7d8d
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
This reverts commit 75cc68bce9.
From the latest code tests, this commit is not required.
Change-Id: Iad8e43fe119dee15de5e9b517df25a41fa71742c
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
drm_format_info can't offer yuv afbc bpp info, so we add this
interface to replenish it.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ib4d5f804b2ccdc20909420acd4911aa159d5a6fc
clk init on time_init() which is before pure_initcall.
So call rockchip_soc_id_init() before call soc_is_rk3308b().
Change-Id: Iece3673bc7309ef9193df99f2a95e4b930613a3e
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
