Rechange the emmc aliase to mmc2 to be same as other rockchip's chips,
so the android application can process the emmc property of all chips
in a uniform manner.
Signed-off-by: Wenping Zhang <wenping.zhang@rock-chips.com>
Change-Id: Ia092ec08552e360e7fc5dc271dbb69edc08bd486
The usb driver will alloc from the cma default memory pool, when it's
limited to 32bit, the cma default memory should limit to dma32.
Change-Id: Ibd91f3158af6eae98d899018685e03e8f47e75a9
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
To use tsadc_shut_m0 function, tsadc must switch to cru_shut_mode,
because tsadc_shut signal have to go through the cru to get to tsadc_shut_m0 signal.
Refer to "10.10.10.81\技术文档\thermal\rk3568_tsadc_shut.png" for details.
Change-Id: I0528917efe2f5ea6f002ebf1608815eb01f552c0
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Now we use U-Boot to write the MAC address into DTB, to
solve the problem of getting the MAC address in the vendor
partition too late at the kernel level, so the Ethernet
alias is added for U-Boot to quickly find the gmac DTB node.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I603946b27ab4668ed5ff4dbb629f3ed9b8741b08
Now we use U-Boot to write the MAC address into DTB, to
solve the problem of getting the MAC address in the vendor
partition too late at the kernel level, so the Ethernet
alias is added for U-Boot to quickly find the gmac DTB node.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ibeae8b4cc09bbf3cfb7b64e51f6f6aa35820bf0d
Donot pull up BT uart pin before rtl87xx power on.
Signed-off-by: Longjian Lin <llj@rock-chips.com>
Change-Id: I562e4c403f2a56f9253ff677d78d9056cd98a54d
This reverts commit 72dc50cd92.
As the system monitor support changing thermal governor and managing
cooling devices, there's no need to export system monitor devices to
thermal framework.
Change-Id: I2ee0314d6f3b342f2c7f41f7fafbb0074555759d
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Add support to change thermal governor to user_space, and the system
monitor will manage cooling devices.
Change-Id: I6b9a51a6ee4ff1f3414a133f157e3bd05d51fcda
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
As dev_pm_opp_check_rate_volt() is implemented in file driver/opp/core.c
by rockchip, it is unsupported for gki.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I13b7b916b1b1310cf5f421e98417bdb4fc1a953a
The cpufreq core now takes the min/max frequency constraints via QoS
requests and the CPUFREQ_ADJUST notifier is removed.
The devfreq core now supports limiting the frequency range of a device
through PM QoS make use of it instead of disabling OPPs that should
not be used.
Change-Id: I3e909bd6a1ba77e565ebb0e4870f79f1e0724b46
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
fix the dclk polarity in the driver to avoid incorrect
configuration, even if we can configure through attribute
pixelclk-active in dts.
Change-Id: Ie3861206d2f6312ef252df87ecb49dd7d5f0ba9b
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
This patch adds support for Synopsys Designware MIPI DSI host IP
used on RK3568 SoC.
Change-Id: Ie3bed6bf8cebf32d9fb3e26ad71eba393cbdffe8
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
According to gki commit b4518aa55c ("ANDROID: GKI: Enable BOOT_CONFIG").
To enable androidboot.<name> and other parameters to be passed through
it, instead of abusing the kernel cmdline.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I0a6cb5c38d949b9bcaa7e70eccc6f191eecc3d91
The current output code only supports connection to drm panels.
Add code to support drm bridge, to support connections to
external connectors.
Change-Id: I775244b7183692f07b74123fa43c8bb958525087
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Not having an endpoint bound in DT should not cause a failure here,
there are fallbacks. So explicitly accept a missing endpoint.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Iea7e2456de05b76cf6d94232ab9bb75425cfffc0
Many TCON devices include an embedded LCD panel self-test mode.
This mode is designed to help system integrators identify
the root cause of abnormal display operation, without the use of
complicated debug tools.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I19770c7488d43e2486c5fde5cc0a5b345e5be0eb
On an eDP connection, the eDP sink must operate only in Enhanced Framing
Mode. The Source must send only Enhanced Framing on the main link, and
must only write a '0' to DPCD 00101h: LANE_COUNT_SET Bit 7:
ENHANCED_FRAME_EN bit.
Independent of method used, DP1.2-compliant eDP Receivers shall indicate
any eDP protocol differentiation method they support through the
Receiver Capability Field of DPCD (DPCD:0000Dh).
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I38e30426924bed531047a2d41b812d697d9f9838
Panel Self Refresh (PSR), originally introduced in eDP v1.3, is an
optional feature for Source and Sink devices.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I39c357d7caefc087241407a7d6b452e47e16eb9a
The analogix_dp_transfer() will return -EBUSY if num_transferred is zero.
But sometimes we will send a bare address packet to start the transaction,
like drm_dp_i2c_xfer() show:
......
/* Send a bare address packet to start the transaction.
* Zero sized messages specify an address only (bare
* address) transaction.
*/
msg.buffer = NULL;
msg.size = 0;
err = drm_dp_i2c_do_msg(aux, &msg);
......
In this case, the msg->size is zero, so the num_transferred will be zero too.
We can't return -EBUSY here, let's we return num_transferred if num_transferred
equals msg->size.
BUG=chrome-os-partner:57501
TEST="gooftool probe --comps display_panel"
Change-Id: Ie09f26b2c31e2406d21233afd8677337de5e77f2
Signed-off-by: zain wang <wzz@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9569045/)
Reviewed-on: https://chromium-review.googlesource.com/414674
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: 征增 王 <wzz@rock-chips.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
This patch adds support for Analogix eDP TX IP used on RK3568 SoC.
Change-Id: Ieb89906cba5bc569ed8c476fecd00f6035a7f582
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Ensure the pclk is enabled when register access occurs.
Change-Id: Id108a04aed8424725dcc02dec9fe46bfc724c09b
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Background:
- EDP software register bank is on the EDP 24m clock domain;
- CPU access EDP software register bank, need to go through EDP APB
read/write bus and EDP internal read/write bus;
- EDP APB read/write bus is on the EDP pclk clock domain;
- EDP internal read/write bus is on the EDP 24m clock domain;
- Asynchronous logic circuit is added between APB read/write bus and
Internal read/write bus;
Issue:
There is a bug on the Asynchronous logic circuit between APB read/write
bus and Internal read/write bus; This bug will be random to cause the
following wrong control/address signals sequence happen;
- For write, maybe wrong register address is wrote in;
- For read, maybe wrong register address is read out;
Workaround:
- For CPU write EDP register operation, write any register need
following three steps,
1): Read EDP_BASE+0x00 dummy register firstly, latch the dummy
register address on Reg_Address bus, to avoid next step write to
wrong register to cause function register overrun;
2): 1st time to write the EDP register you want to operate,
to latch the real write address on Reg_Address bus;
3): 2nd time to write the EDP register you want to operate,
to make sure the data is write on the real write address;
- For CPU read EDP register operation, read any register need following
two steps,
1): 1st time to read the EDP register you want to operate, to latch
the real read address on Reg_Address bus;
2): 2nd time to read the EDP register you want to operate, to make
sure the data is read out from the real read address;
Change-Id: I4a87d3883efe94d32ccf8809edb5b9d869670d2d
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
The interrupt is requested before the device is powered on and
it's value in some cases cannot be reliable. It happens on some
devices that an interrupt is generated as soon as requested
before having the chance to disable the irq.
Change-Id: I889c069239d005ab0a3fb4eb36123608ec81d9ab
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
