The gpll clock has not yet been created when its children do enable and
prepare in cru critical talbe, so move its children into pmucru critical
talbe that the gpll clock has been created before its children do enable
and prepare.
Change-Id: If5243326bf1d3c926bb1bb12e56e4b9fc9282762
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
If xin32k use the rk808_clkout1, rk808 init is too late,
xin32k enable count and prepare count is not match with it's child clk.
Change-Id: Iec5d1f91b2289b18f41b4d915e6859154a5b7635
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
It needs to contains rate and mux clk for gpu composite clk, so that
the clk_composite_set_rate_and_parent function can be called.
Change-Id: I9818df2adbbcf40f616d2ca230cd83ea1ef2c14f
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
If the regulator is shared between several devices then the lowest
request voltage that meets the system constraints will be used.
Change-Id: Icb6afcb571bddd6709d352dfad8fc2da80567bc0
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
If there is only one opp whose frequency is equal to the initial value
in opp table list, the GPU voltage domain will keep the initial voltage,
it may be too large.
Change-Id: If2ae1c876de185d810e05296b1b9e98855c3ef48
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
drivers/regulator/syr82x.c:451:3: warning: this if
clause does not guard... [-Wmisleading-indentation]
Change-Id: Ibdb1f6f903d1e0dece7b58aa3ec89d075e6d5b79
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
drivers/input/touchscreen/cy8c_touchpad.c:77:20: warning: xfer_msg[1].flags
is used uninitialized in this function [-Wuninitialized]
Change-Id: I2d1f199f098b38af92037e2ebbd63c05fc4a1f35
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This patch adds the function of mipi-dphy TX1RX1 for RK3288, the
mipi-dphy TX1RX1 is matched when "txrx_base_addr" is valid.
Change-Id: I01640925157a7082e942188b29f6bbf1318cf3d5
Signed-off-by: Wen Nuan <leo.wen@rock-chips.com>
This reverts commit cbd1d90f72.
8588d88f1a ("ANDROID: android-base.cfg: add CONFIG_IKCONFIG option")
This adds CONFIG_IKCONFIG and CONFIG_IKCONFIG_PROC options, which are a
requirement for the O release.
Change-Id: I438ade881219034618afb4cd5174bf750a79d319
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This reverts commit 95bc3a8935.
8588d88f1a ("ANDROID: android-base.cfg: add CONFIG_IKCONFIG option")
This adds CONFIG_IKCONFIG and CONFIG_IKCONFIG_PROC options, which are a
requirement for the O release.
Change-Id: Id02fde91ed902f266ff5c81ec04e2427a2877847
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
e8f5f841b764 ("remove CONFIG_ANDROID_LOW_MEMORY_KILLER requirement")
Kernel configuration options should include either
CONFIG_ANDROID_LOW_MEMORY_KILLER for in-kernel lowmemorykiller driver
to be used or a combination of CONFIG_MEMCG and CONFIG_MEMCG_SWAP
if userspace lmkd is preferred. It is not currently possible to express
this logical requirement in the config fragment so the
CONFIG_ANDROID_LOW_MEMORY_KILLER requirement is simply
removed for now.
Change-Id: I9cea0552a285ac635fc44f4b45762988e423d7db
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
e8f5f841b764 ("remove CONFIG_ANDROID_LOW_MEMORY_KILLER requirement")
Kernel configuration options should include either
CONFIG_ANDROID_LOW_MEMORY_KILLER for in-kernel lowmemorykiller driver
to be used or a combination of CONFIG_MEMCG and CONFIG_MEMCG_SWAP
if userspace lmkd is preferred. It is not currently possible to express
this logical requirement in the config fragment so the
CONFIG_ANDROID_LOW_MEMORY_KILLER requirement is simply
removed for now.
Change-Id: I69b9682029a50f4579f3ba11e6a9a497c5a51c28
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
As the edp_hpd pinctrl is reused by hdmi-cec. So the rk3399 will hit the
pinctrl register failed on bootup.
Says: the failed log:
[0.927577] rockchip-pinctrl pinctrl: pin gpio4-23 already requested by
ff940000.hdmi; cannot claim for ff970000.edp
[0.928519 ] rockchip-pinctrl pinctrl: pin-151 (ff970000.edp) status -22
[0.929112] rockchip-pinctrl pinctrl: could not request pin 151
(gpio4-23) from group edp-hpd on device rockchip-pinctr
That will cause the edp can't work on rk3399 SoCs.
Fixes: commit
6e4eaff822 ("arm64: dts: rockchip: add HDMI cec support for rk3399")
Change-Id: I8ba20db55025e33c082beda5160e0398f1681766
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
On rockchip platform, hdmi input format is YCbCr444 when output mode
is YCbCr422. Then the value of HDMI_TX_INVID0 on YCbCr422 is same as
the value of YCbCr444, both is 0x09/0x0b. This make enc_out_bus_format
stroed in struct hdmi_data is wrong, which is MEDIA_BUS_FMT_YUV8_1X24
or MEDIA_BUS_FMT_YUV10_1X30.
When android set enc_out_bus_format to YCbCr422, dw_hdmi_setup will be
called and logo will flash.
This patch use colorspace restored in HDMI_FC_AVICONF0 to distinguish them.
Change-Id: I6b913951b58fb47628617c11d6059bc1be4e370a
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Because it will cause CPU hangs on, so disable the reset temporarily.
Change-Id: I612be4b47145fd1ebf8d8e5d44270f26151768fa
Signed-off-by: Zhong Yichong <zyc@rock-chips.com>
f3d9c312b8 ("Implement memory_state_time, used by qcom,cpubw")
New driver memory_state_time tracks time spent in different DDR
frequency and bandwidth states.
Memory drivers such as qcom,cpubw can post updated state to the driver
after registering a callback. Processed by a workqueue
Bandwidth buckets are read in from device tree in the relevant qualcomm
section, can be defined in any quantity and spacing.
The data is exposed at /sys/kernel/memory_state_time, able to be read by
the Android framework.
Functionality is behind a config option CONFIG_MEMORY_STATE_TIME
Change-Id: Ic3b0b631efd697713360f193ede440cd9ad3bc29
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
f3d9c312b8 ("Implement memory_state_time, used by qcom,cpubw")
New driver memory_state_time tracks time spent in different DDR
frequency and bandwidth states.
Memory drivers such as qcom,cpubw can post updated state to the driver
after registering a callback. Processed by a workqueue
Bandwidth buckets are read in from device tree in the relevant qualcomm
section, can be defined in any quantity and spacing.
The data is exposed at /sys/kernel/memory_state_time, able to be read by
the Android framework.
Functionality is behind a config option CONFIG_MEMORY_STATE_TIME
Change-Id: I4391cc3ed42c9f332bce4a7809c6f120e2798dae
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
If we power off the SoC LOGIC rail in S3, we can find that the
Type-C PHY can't initialize correctly after system resume with
error log looked like this:
phy phy-ff800000.phy.9: phy poweron failed --> -110
dwc3 fe900000.dwc3: failed to initialize core
dwc3: probe of fe900000.dwc3 failed with error -110
It's because that the field of usb3tousb2 in GRF_USB3PHY0/1_CON0
is reset to 1 after power off the SoC LOGIC, which means that the
pipe interface is blocked between Tpye-C PHY and usb3 controller.
And after system resume, the rockchip_usb3_phy_power_on() will call
the tcphy_cfg_usb3_to_usb2_only() to clear the usb3tousb2 bit and
enable the usb3 host again. If we clear the usb3tousb2 bit before
pipe ready, it may cause waiting for pipe ready timeout.
Note that the RK3399 TRM suggests that we should keep the whole usb3
controller in reset for the duration of the Type-C PHY initialization.
However, it's hard to assert the reset in the current framework of
reset. And according to the TRM, it doesn't require that we should
clear the usb3tousb2 bit before pipe ready. So let's enable the usb3
host after pipe ready to avoid the Type-C PHY initialization failure.
BUG=b:62644399, chromium:783464
TEST=run suspend_stess_test on Scarlet, usb device can work after resume
Change-Id: Ie597cbe35568c390460aa2fdbad0e66c6104c8d2
Reviewed-on: https://chromium-review.googlesource.com/896908
Commit-Ready: Brian Norris <briannorris@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: William Wu <william.wu@rock-chips.com>
If we power off the SoC LOGIC rail in S3, it seems that the host
controller comes back in an undefined state, such that the Type C PHY
can't initialize correctly. We need to toggle the USB3-OTG reset before
trying to initialize the PHY, or else it often times out.
Note that the TRM suggests we should be asserting this reset for the
duration of the PHY initialization, but we're still skeptical about
that, and we haven't yet found a case where this seems to have mattered.
Besides, this approach is much easier.
The dwc3 core is going to reinitialize the controller at suspend/resume
anyway (including a "soft reset"), so it should be safe to do this,
regardless of whether the system actually powered off the USB logic.
For hygiene's sake, it's good to wait some small bit of time in between
asserting/de-asserting this reset. Might as well apply this to both
instances of this reset.
BUG=b:62644399
TEST=suspend/resume scarlet with LOGIC disabled in S3; USB comes back OK
also test suspend/resume on kevin for USB regressions
Change-Id: I5b5354d0fb9c7ed9d2c9044ddfbb5f7709884fb7
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/877404
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Base on the rise time of scl test, the scl frequecny could be
increased to 400k.
Change-Id: I17f858b28ed11992411c52e5f83424b0187d097c
Signed-off-by: David Wu <david.wu@rock-chips.com>
Base on the rise time of scl test, the scl frequecny could be
increased to 400k.
Change-Id: I9af57e13a97f0866ec4f0dd295f9bcf4cbeee304
Signed-off-by: David Wu <david.wu@rock-chips.com>
