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7490a94de216328f69fc9ee6f85146980a752017
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562 Commits

Author SHA1 Message Date
Finley Xiao
0e7eba3141 clk: rockchip: rk3308: Rename gmac to mac 
Change-Id: I31e9fddcffde824c2b41bd3eddccf3a995cfb913
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2018-03-14 14:42:20 +08:00
Finley Xiao
d65b1d2ec8 clk: rockchip: rk3308: Add dmac clocks 
Change-Id: I63e30bb23f6bc61f1dcc189e3bc43a6f1bb57f3f
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2018-03-13 13:56:09 +08:00
Finley Xiao
229a58abce clk: rockchip: Add dt-binding header for rk3308 
Add the dt-bindings header for the rk3308, that gets shared between
the clock controller and the clock references in the dts.

Change-Id: I9c6ea1228417f07603d89f810726e9cdffd2a10a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2018-03-06 18:17:49 +08:00
Finley Xiao
9d6d0e8f7e clk: rockchip: px30: Add clock id and CLK_SET_RATE_NO_REPARENT for uart1 
Change-Id: I1115c5cdeca962b3281297eec0c1d56a1fa7d023
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2018-03-05 14:54:02 +08:00
Finley Xiao
fda77d7005 clk: rockchip: px30: Add clock id for aclk_bus_src and aclk_peri_src 
Change-Id: I3467b4f799a6f5402eed3d20e4bd2c02ae30c92f
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2018-02-22 10:55:21 +08:00
Finley Xiao
884b0673a7 clk: rockchip: rk3288: Add TSP clock 
Change-Id: I02185c5ab7a1072d271cd51161f6d4b05d327673
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2018-02-10 09:04:17 +08:00
Finley Xiao
a250f09aff clk: rockchip: rk3128: Add sclk_hsadc_tsp 
Change-Id: I842869a7ea79730daa6616f1cf2a8f5db7165ceb
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2018-02-10 09:04:17 +08:00
YouMin Chen
8865f61ad2 PM / devfreq: rockchip_dmc: add support for px30 
Change-Id: I225088ce179f9b9cd62fce256b87bccb591fd2b2
Signed-off-by: YouMin Chen <cym@rock-chips.com>
 2018-02-08 14:52:32 +08:00
YouMin Chen
326d6f59d1 clk: rockchip: px30: Add SCLK_DDRCLK for dmc 
Change-Id: I03d6c18829f8895c28bbaef883e187304c48f9aa
Signed-off-by: YouMin Chen <cym@rock-chips.com>
 2018-02-08 14:52:26 +08:00
Liang Chen
adbf52abda clk: rockchip: rk3228: add clk_ddrc for devfreq of ddr 
Change-Id: I3771e2ef68ab3fa8ad1b7d61a84c7181c693c60f
Signed-off-by: Liang Chen <cl@rock-chips.com>
 2018-02-08 09:35:17 +08:00
Xinhuang Li
1cfda2f55e clk: rockchip: rk3228: Add clock id for pclk_acodecphy 
Change-Id: I289f2c2681e187eaed0cda1561544581409ffd07
Signed-off-by: Xinhuang Li <buluess.li@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2018-02-07 12:03:35 +08:00
Finley Xiao
b503ff5697 clk: rockchip: rk3368: Add clock id for tsp 
Change-Id: I79a423f93f991aab43922e58ce34eac1754304e2
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2018-02-02 09:46:34 +08:00
Tao Huang
f9eefeeaa7 rk: add SPDX license identifier to files with no license 
Change-Id: I754250669891307b0deab2bdab1bd01512713f79
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
 2018-01-31 20:56:06 +08:00
Finley Xiao
7bd13a986e clk: rockchip: px30: Modify SRST ID according to latest document 
Change-Id: Idb6b845581a18082f851c4b67e1ef5bd3a5bc886
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2018-01-31 17:11:06 +08:00
Finley Xiao
545c52479c clk: rockchip: px30: Add clock id for pclk_otp_phy 
Change-Id: If9c368c6ff93d31f306ab16dbf49dd698f320f72
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2018-01-26 14:25:57 +08:00
Finley Xiao
38cd02b946 clk: rockchip: px30: Add pclk for cif and isp 
Change-Id: Ied25f2c6746e7cc233c4c22436f45ba82900631a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2018-01-24 10:36:56 +08:00
David Wu
f37ae45b20 dt-bindings: clock: px30-cru: Rename the gmac reset 
Change-Id: I91976f4f4fe4e8b81a5520a12995c317c16b0190
Signed-off-by: David Wu <david.wu@rock-chips.com>
 2018-01-24 09:45:19 +08:00
Finley Xiao
db52b49619 clk: rockchip: px30: Fix parent clk for nand, sdio and emmc 
Change-Id: I5723e114871d03d271a398a55af97474e08a61e1
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2018-01-23 14:22:18 +08:00
Finley Xiao
8b31d4d2da clk: rockchip: px30: Modify clk tree according to latest document 
Change-Id: Ib8d983509792b13c1cc84c78af0f572b89053cc7
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2018-01-18 16:52:22 +08:00
Hecanyang
4807c45f72 PM / devfreq: rockchip_dmc: add support for rk3328 
This adds the necessary data for handling dmcfreq on the rk3328

Change-Id: If4cff5cc372f80b6776a7272a1bff54abef2cf33
Signed-off-by: CanYang He <hcy@rock-chips.com>
 2017-12-28 08:48:54 +08:00
Wyon Bi
d04dec1a54 clk/rockchip: add cru support for rk618 
Change-Id: I223c85194f62fec2c22c2a013466b767a1128f9c
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2017-12-21 10:30:28 +08:00
Finley Xiao
09f340ba86 clk: rockchip: px30: Fix aclk and hclk for vpu, sdcard and crypto 
Change-Id: I6f3d77033b493bdaac9d05c2be5eea38290a089e
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2017-12-13 18:32:21 +08:00
Finley Xiao
3cb6cc8a59 clk: rockchip: rk3066a: Rename i2s hclk id 
Change-Id: I0a5ccf1846950353ea6fc6980c1c4a4fb3457fd1
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2017-12-07 18:57:44 +08:00
Elaine Zhang
15f1fd6c6a clk: rockchip: add dt-binding header for px30 
Add the dt-bindings header for the px30, that gets shared between
the clock controller and the clock references in the dts.
Add softreset ID for px30.

Change-Id: I643f5e40cf77fb5c3aeb41392172da79194d54c1
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2017-12-07 15:07:03 +08:00
Finley Xiao
e62d8931ec clk: rockchip: rk3288: Add id for i2s_src 
Change-Id: I0d15dd656e96a3905012d42fef6640e152838888
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2017-12-05 17:40:00 +08:00
Dalon.zhang
38c93fe590 clk: rockchip: rk3288: add PCLK_VIP and PCLK_VIP_IN 
Change-Id: I51357dc00c842c7ecb49b13580e59f33d87d21b8
Signed-off-by: Zhang Yunlong <dalon.zhang@rock-chips.com>
 2017-11-27 19:36:16 +08:00
Caesar Wang
2586696eee clk: rockchip: export the i2s sclk parent clocks for rk3036 
Add the SCLK_I2S_PRE and SCLK_I2S_FRAC id for i2s sclk.

Change-Id: Ic66291f2a76ec5c2a47e9721ad6f37922264fd42
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
 2017-11-17 17:44:17 +08:00
Finley Xiao
390766191a clk: rockchip: rk3066a: Add some clock IDs 
Change-Id: I57f948a425936e0f69b63e7ded86c8d2cdf84148
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2017-11-07 09:41:57 +08:00
Randy Li
278e91efa2 clk: rockchip: rk3036: export the hevc core clock 
The clock hevc core will be used to drive the hevc decoder.

Change-Id: Ic1298ce1edd07f86e5c243e3a2c9876481f4cba9
Signed-off-by: Randy Li <randy.li@rock-chips.com>
 2017-10-20 17:48:34 +08:00
Jacob Chen
4a4a40b964 clk: rockchip: associate SCLK_MAC_PLL on rk3288 
see:
http://elixir.free-electrons.com/linux/v4.8/source/Documentation/devicetree/bindings/net/rockchip-dwmac.txt#L32

Change-Id: Ibf94d88219b13f5dd16cfdeb02d1b255e695399f
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
 2017-09-29 10:27:11 +08:00
Elaine Zhang
1b523997b3 clk: rockchip: rk3399: fix up the clk tree description for clk_uart4 
slove clk_uart4 set rate error.

Change-Id: Icf8f36a5c68658ed92a1b794dc68f37c729d2646
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2017-09-20 10:29:37 +08:00
Sandy Huang
1e23e1f0b2 clk: rockchip: rk3128: add clk gate for PCLK_MIPIPHY 
Change-Id: Icf55c315edc9514a23d00433ffe56c864ad7f3d8
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
 2017-08-24 11:31:50 +08:00
Elaine Zhang
428fab17d9 clk: rockchip: rk3228: add SCLK_SDIO_SRC clk id 
This patch exports sdio src clock for dts reference.

Change-Id: I3e83cce4da3d82af4b18df43ecd51c504d308c02
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2017-06-16 14:14:29 +08:00
WeiYong Bi
7df0bff9b6 clk: rockchip: rk3228: export hdmiphy clock 
Change-Id: Ib7acd4c2f576ad320e069ab2bd9137156062e2d9
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
 2017-06-06 15:08:21 +08:00
Elaine Zhang
7c7c946356 UPSTREAM: clk: rockchip: add dt-binding header for rk3128 
Add the dt-bindings header for the rk3128,
that gets shared between the clock controller and
the clock references in the dts.
Add softreset ID for rk3128.
And it also applies to the RK3126 SoC.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit b20841b9e0)

Change-Id: I70c055570319abe4547ac2a42b9139c7248abb13
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2017-06-05 14:30:29 +08:00
Finley Xiao
3aacbd51b7 PM / devfreq: rockchip_dmc: add support for rk3368 
This adds the necessary data for handling dmcfreq on the rk3368.

Change-Id: Ie202cbaa3b27e52b22a5efc57c6e108fbd03a20a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2017-05-04 12:02:45 +08:00
Elaine Zhang
94fb9cc3be clk: rockchip: rk3228: Perfect clock description 
1 Add some necessary clk ID.
2 some clks add CLK_IGNORE_UNUSED flag
3 add some critical clk

Change-Id: If52699b4d5f430413b06084b7d21fb1afd4539dd
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2017-05-03 17:18:12 +08:00
Finley Xiao
0d9aeb389a clk: rockchip: add SCLK_DDRCLK id for rk3288 ddrc 
Add the needed id for the ddr clock.

Change-Id: I9578decd2348a35a6e9c4cc3527375d4d02a2af6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2017-05-03 17:15:23 +08:00
Elaine Zhang
40b3da4859 clk: rockchip: add ACLK_VIO0\1 HCLK_VIO id for rk3288 vio 
Add the needed id for the vio clock.

Change-Id: I2c4009d8214e1560da1213f224610882c2cd06e7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2017-04-11 16:39:29 +08:00
Sugar Zhang
152ba302e7 dt-bindings: clock: rk3328: add pclk_acodec id 
Change-Id: I3b0e2d2da5f919ed88f599823784aefa5e9a330c
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
 2017-04-10 14:27:14 +08:00
Sugar Zhang
25f584e048 dt-bindings: clock: rk3328: fixup HCLK_I2S1 id 
Change-Id: I40e6543988e1c1a0cbb475eacbb5f3f985da55e7
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
 2017-04-10 14:26:54 +08:00
Elaine Zhang
15e1a8fff4 clk: rockchip: rk3368: add aclk_cci_pre ID 
Change-Id: I855e79023a9e244c2db37af88a075a4ef4c36aec
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2017-04-07 18:51:15 +08:00
Finley Xiao
fe99293b22 clk: rockchip: add SCLK_DDRC id for rk3368 ddrc 
Add the needed id for the ddr clock.

Change-Id: Ib2a4d8dffef5b393e294df49a925577f14306e72
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2017-03-29 10:51:59 +08:00
Frank Wang
696b3f25a2 clk: rockchip: rk3288: add gate id of hclk_usb_peri for usb otg 
Change-Id: Ib45f6d97ec81329ec9a4a19e9e836efa0ea61fe2
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
 2017-03-28 17:27:01 +08:00
Elaine Zhang
a4d5799749 clk: rockchip: rk3368: export SCLK_TIMERXX id for timers 
Change-Id: I77fa21f29e7ff46e1bd4150845dfafe0a83b84c1
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2017-03-16 08:50:17 +08:00
Finley Xiao
3125e80cd5 clk: rockchip: add ids for efuse pclk on rk3368 
Adds new ids for the pclk supplying the efuse on rk3368 socs.

Change-Id: I69f0daf402d62079e47d8df8f6e9bef0b274239f
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2017-03-14 10:28:27 +08:00
Mark Yao
5334ebb963 rockchip: clk: rk3399: default enable dual pll for vop 
Change-Id: I88a2a549eaafa91e4159f262a5f5838c834a89e9
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
 2017-02-22 14:24:04 +08:00
Elaine Zhang
a82aa2fad3 dt-bindings: clock: rk3328: add clk_mac2io_ext ID 
Change-Id: I1f17c50020d5f37f5cfd6a4d0ecfc195bad2687d
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2017-02-07 17:39:11 +08:00
Jacob Chen
aa4ac52a97 clk: rk3288: correct cif_out to vip_out 
we already have vip_src and sclk_vip_out defined, which are the clocks
we add as cif_out, so let's correct it.

Change-Id: I952b1490a882d290aa36d9629aeb32eee22ce8b3
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
 2017-01-19 10:08:10 +08:00
Elaine Zhang
ec7c587fe9 clk: rockchip: fix up the clock controller for rk3328 
According to Heiko's advice,fix up some code style,
reference the other clock drivers for indentation.
remove grf clk init and use muxgrf to describe.
fix up the pll parent only xin24m.
fix up these *_sample error description.
add mac2io and mac2phy clk id.
moving the clock-ids a bit more together.

Change-Id: I96273a6bf808841d0488dd9db461efdffc82a99f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2017-01-06 10:50:11 +08:00