Since the interrupt status of FUSB302 is R/C scheme, the interrupt
may miss between the top half and the bottom half (work), so make
the irq work to run with real time priority and get scheduled in time.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I315ea7689c964a866f6578d25db85af4a26cd860
aiq no set readback mode and isp set auto readback mode
echo Y > /sys/module/video_rkisp/parameters/rdbk_auto
Change-Id: I78541b7a88bbfa300323a3c4ef4f8f512d7208bf
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
This is used, for example, when there are several multiplexers
on the same bus and the devices on the underlying buses might
have same I2C addresses.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Idf2ff4dad5dabffaf7065a3f5d39cf3621b574a1
This is used, for example, when there are several multiplexers
on the same bus and the devices on the underlying buses might
have same I2C addresses.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I33e8206c55785808e2e29128a572ea657cb45f62
Adds recommended N and Expected CTS Values for FRL Mode
which defined in chapter 9.2.2 of HDMI Specification 2.1.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I1a21a111a65beeb024e5740c8bd231f9f534c1b5
This patch workaround for no sound issue on Hisense TV which
seems to need AUDI ACR packet when initial stage.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I192b631b29d33ad6571f70e062788c45b917803c
Keep ACR, AUDI, AUDS packet always on to make SINK device
active for better compatibility and user experience.
This also fix POP sound on some SINK devices which wakeup
from suspend to active.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I6bb80a85a7ce0ba7046b4ac7bb7d75c38fcd95f3
The HDMI controller ignores the first FRAME_SYNC cycle data,
Lost one frame is no big deal for LPCM, but it does matter
for Bitstream (NLPCM/HBR), So, padding one frame before xfer
the real data to fix it.
Suggested to stop audio source before HDMI configure to make
sure audio data integrity on HDMI-PATH-ALWAYS-ON situation.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I35119736e81dc4687408a59502b9a7ef2f87d3a5
This patch introduce function always-on which allow controller
to keep clk (BCLK/SYNC) always-on.
In HDMI audio situation, we found some SINK devices need SOURCE
to keep xfer ACR, AUDS packet always on to fix sound compatibility.
And the AUDS packet is drived by audio source (e.g. I2S).
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I4c7aceb504e3b0820c329b398812d04f6a88993d
Explicitly delay 1 usec for dma to fill FIFO,
though there was a implied HW delay that around
half LRCK cycle (e.g. 2.6us@192k) from XFER-start
to FIFO-pop.
1 usec is enough to fill at lease 4 entry each FIFO
@192k 8ch 32bit situation.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I9eebfcfa6a3fc73a75b2ea9c700131b5cd366bde
Set dma maxburst per FIFO waterlevel for better performance
on high bit-rate situation, such as 192k 8ch 32bit situation.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ib8d7596e2f43fa8efec10ce045bb3225e3873070
This patch simplify xfer and reset routine. and prepare
for better support for always-on function.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I0d8a2588566783e604dfec26deaf3bfca9178deb
If we specify the property of acodec "rockchip,no-hp-det", we
shouldn't queue the hpdet_work that is without initialized,
and the dwork timer->function is NULL.
The crashed log:
===
[ 0.666484] ------------[ cut here ]------------
[ 0.666536] WARNING: CPU: 1 PID: 1 at kernel/workqueue.c:1657 __queue_delayed_work+0x51/0xd8
[ 0.666553] Modules linked in:
[ 0.666586] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.10.110 #168
[ 0.666602] Hardware name: Generic DT based system
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Change-Id: I66de7c031c6d7373eb77e65448771eb183e0888b
The pin range from GPIO0_B4 to GPIO0_D7 for rk3588 SoCs should set two
registers for iomux, since each of them has 8 bits width.
This patch fixes a issue when reset the iomux from a value from larger
than 8 to a value littler than 8, the high 4 bits should be reset to
'0'.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I61196f78ceb08ed47b26374c6f1ca7031f15b9d9
GMSL2 serializers include a novel line-fault detection circuit that
detects and reports open-circuit, short-to-battery, short-to-ground,
and line-to-line short. The line-fault monitor is disabled by default,
and configuration options are available through registers. Its status
can be read by register.
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: Ie548d25a8492f0ff883cc777c3a14049d25dda9a
GMSL2 serializers include a novel line-fault detection circuit that
detects and reports open-circuit, short-to-battery, short-to-ground,
and line-to-line short. The line-fault monitor is disabled by default,
and configuration options are available through registers. Its status
can be read by register.
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: Iad44a7d2a56992f2906376b9a07e708c8f37c05b
when a request is being submitted, if one of the job commits fails,
the submission of the request is aborted and return an error.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I15c0271c95a66288f1232c9e33d731e5c14741c8
kernel_read()/kernel_write() are missing from GKI symbol list.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: Id8c15e682e6187f551aa48ee28d23944d71b72f6
CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP is not need for now.
Signed-off-by: Elon Zhang <zhangzj@rock-chips.com>
Change-Id: I6f0d06f8caae764839d87fd3dbcbe35c10140437
The "amp-shared" means the other processors might use I2C at the same
time, make sure that the other processors finish.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: I43fd964a684e54baf1e600776cbf27b2fe7d6df6
1. modify max and min gain value.
2. add digital_gain_reg for gain setting
Signed-off-by: Shiqin Chen <chensq@rock-chips.com>
Change-Id: I690ba934964fea8c1052ffdf10438016094baac6
Fix the use of job->ret that has been released when returning abnormally.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I93f2fd89c16790889aabcda43f5a848a999d1277
The LSM6DSR has an ODR selection ranges from 12.5 Hz to 833 Hz,
remove the fix ODR selections in the ODR table.
Signed-off-by: Jason Zhang <jason.zhang@rock-chips.com>
Change-Id: I1eca8a4d2fb07370750b9f9aeb3f3f3781bfd68e
The sequence of hw->lock and hw->page_lock in
st_lsm6dsr_update_watermark and st_lsm6dsr_fsm_init are in
reverse, which may results in deadlock.
The fifo water mark is held by iio_dev->mlock, Remove hw->lock
in st_lsm6dsr_update_watermark.
Signed-off-by: Jason Zhang <jason.zhang@rock-chips.com>
Change-Id: I9a1f60cf0ba4444f285ecb95fb37745fbf45e609
