This patch make rockchip_pcm.c compiled depends on SND_SOC_ROCKCHIP,
because all the dai of rockchip will switch to use it, and we can
do much more customize, such as minimize the prealloc buffer size.
Change-Id: Ia7a3923db6760273d2291b41c194f28b43de83b2
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
1.improve buf manager to aovid memleak and buf lost
2.don't refresh overlay image when overlay disabled
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
Change-Id: Ib3ef89752549cf89230827ed91440b831a0544e2
The CLK_SET_RATE_PARENT flag make the parent clock and the child clk is 1:1.
If the DCLK frequency is too low, the PLL frequency will be very
low, which will affect the output waveform quality of PLL, and PLL
locking may be abnormal, so add a new COMPOSITE_DCLK clock-type to
handle that.
Change-Id: Id95a14c0fbd0ad2799a77190a5d21dd490c6ede8
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
1.full/a2/du/du4: check part also
2.auto mode use full gc16 waveform to reduce ghosting
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
Change-Id: I3a2156ccecc5d630b1adb2425d647fb8efb090be
Add CLK_GATE_NO_SET_RATE for gate clks not allowed to support setting
rate.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Iddd1c958661f8ff9217b8781426314b0619367db
The maximum alpha is 255, but after the product of color and alpha
in the blend formula, the final result is >> 8 (/256) instead of
/255, which will introduce errors.
This fix is that when alpha is 0x80~0xff, then +1.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: Ibba964f29a11eb226aa008a0dd5bf89048524b43
Some traditional display devices like use 1024x768p60 resolution, so we
add this mode to default mode when parse edid failed.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ibb67898f8b0cc7b98f988a783f8eb4c28aa18359
Some traditional display devices like use 1024x768p60 resolution,
so we add this mode to default mode when parse edid failed.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I0acd1241d84ae65d415f595d6147fed3da0b2f20
This will used when product use edp2hdmi or edp2vga output.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Idf02a0d1e1bcef579fb3d6117a5e89744bdaac8a
When setting the 16550 serial port baud rate, you need
to configure the UART to loopback mode. After setting
the DLL and DLH, you need to reset the LSR first,
and then configure the MCR to make the UART return
to the normal mode. If you do not reset the LSR
first, an error will occur when the UART RX is still
receiving data.
Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Change-Id: Ia940b278554ef1d4e7a6c4550fe4a4600407a57e
Amend to fix the UAC2 gadget could not be identified on Windows 10 OS.
Fixes: 486bd80e78f4 ("UPSTREAM: usb: f_uac2: adds support for SS and SSP")
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I992af23ab4ac2740a33621d9c3c47368f5135710
This reverts commit 6a1a1cf4e7.
1.Set rk3568 spi node to fall back point
2.Both rk3568 and rv1126's spi is the same design
Change-Id: Ibbb8e4005ad7cd2a6d53eb4c700d657e1f95be7f
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Both rk3568' spi is compatible with rk3036's spi design.
Change-Id: I952beb57c151e77165db781bc17ec782b6bc62a4
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
the sub_dev will be update by list_for_each_entry() and return !NULL
error pointer when no found subdev;
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I8d7db3b66c6c57b986a42cac9ed6eca53b72611e
The current output code only supports connection to drm panels.
Add code to support drm bridge, to support connections to
external connectors.
Change-Id: I775244b7183692f07b74123fa43c8bb958525087
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Validate the cached values of link parameters before
attempting to retrain.
Change-Id: Idf4f8a7c2d85109e05dc7e387f46ddeb55cd0a01
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Split dynamic lane configuration from tcphy_dp_cfg_lane().
Change-Id: Ie4ce3138b30f3f9304daec9a9c582091548c0e60
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
According the CEA-861, HDMI outputs the limited range by default.
Change-Id: I06fc1b92ca15e17fd27f3c09f9ced675f686c15f
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
