From chip design point of view, ATS support wasn't implemented in EP mode,
but leaving ATS cap available for both of EP and RC mode is totally broken
if servers active IOMMU and ATS support.
Reports state the problem are:
(1)When running the rk3588 in endpoint mode, with an Intel host with IOMMU
enabled, the host side prints:
DMAR: VT-d detected Invalidation Time-out Error: SID 0
(2)When running the rk3588 in endpoint mode, with an AMD host with IOMMU
enabled, the host side prints:
iommu ivhd0: AMD-Vi: Event logged [IOTLB_INV_TIMEOUT device=63:00.0 address=0x42b5b01a0]
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I7763f304bb3b71c11a67579803b2531ab7538133
For RK3588/RK3576, eDP IP can support not only eDP v1.3 but also
DP v1.2.
According to the SI test result, the new RBR and HBR pe/vs
configurations can better meet the DP v1.2 signal specification
requirements.
Change-Id: I3dfc1facebe0bf5fb7bc1d35b9fd397aefa71948
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The bridge drivers is various, so the check of switching the
eDP/DP mode may not cover all application scenario.
Therefore, we add a property of the eDP node to support forced
switching to eDP mode, and the DT setting may be like:
&edp {
edp-mode;
};
Change-Id: I4f808b57def701e96d63d2470c2ec904e0ab29a5
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Some bridges support to convert DP into display interfaces that support
the panel, such as RGB, LVDS, MIPI and so on. For instance, the LT7211B
and LT7911D from Lontium can offer this functionality.
Therefore, we add a property of the eDP node to support forced switching
to DP mode, and the DT setting may be like:
&edp0 {
dp-mode;
};
Change-Id: I0f7c2598f86fb9d5ebedc945e3acd66388215d16
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Since the Analogix IP can support both eDP v1.3 and DP v1.2, it is
sensible to first check whether the last bridge is connected to a
panel in order to determine and pass on the eDP/DP submodes to the
PHY, which can help separate the eDP/DP configurations in the PHY
driver.
Change-Id: I86e1c52e15f9348ff9524caaa159f92e5c6fc5de
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
For RK3588/RK3576, eDP IP can support not only eDP v1.3 but also
DP v1.2, which has the different PHY configurations to separate
eDP and DP mode.
Change-Id: I04d72c1230e939b647c5f79c0351f621ade5510d
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The VDD_LOGIC of rk3308-evb-v11 is fixed, so do not enable dmc.
Change-Id: I17bf982d8d4107f8ce474b80c9e80d3e610d6029
Signed-off-by: Liang Chen <cl@rock-chips.com>
The current driver use HDMI hardware's auto CTS mode. We found
that at high sample rates, the auto-calculated CTS value is incorrect,
leading to silent outputs on devices that rely on n/cts to recover
the sample rate, such as TV.
Auto CTS mode was introduced in commit fdbdcc83ff ("drm/bridge: dw-hdmi:
Use automatic CTS generation mode when using non-AHB audio") to handle
cases where audio clock and TMDS clock are not sourced from the same PLL.
However, on RK platforms where both clocks are derived from the same PLL.
This patch adds a "cts-manual" property to allow manual CTS configuration
when clocks are co-sourced.
Fixes: fdbdcc83ff ("drm/bridge: dw-hdmi: Use automatic CTS generation mode when using non-AHB audio")
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I2f52499150d3e37652e21c0b863447e1a6ac5831
Clear the Audio Logic to fix the NLPCM and HBR situation switch.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I98c25e36c76c1308c5b4d50a1d861e3b043e2235
Other types of irq should only be fired during linked state, except
misc irq. Masking it to keep suspend and resume in noirq environment,
otherwise we might occur accessing dbi in irq for hot reset case while
resuming haven't finished, which causing the system hung.
Thread #1 (Suspended : Step)
dw_pcie_read() at pcie - designware.c:106 0xfffffc0106809d0
dw_pcie_read_dbi() at pcie - designware.c:147 0xfffffc0106809d0
dw_pcie_readl_dbi() at pcie - designware.h:315 0xfffffc01068686c
rk_pcie_sys_irq_handler() at pcie - rockchip.c:1,432 0xfffffc01068686c
__handle_irq_event_percpu() at handle.c:156 0xfffffc0100ccd50
handle_irq_event_percpu() at handle.c:196 0xfffffc0100cd03c
handle_irq_event() at handle.c:213 0xfffffc0100cd03c
handle_fasteoi_irq() at chip.c:732 0xfffffc0100d2b00
generic_handle_irq_desc() at irqdesc.h:152 0xfffffc0100cbc70
__handle_domain_irq() at irqdesc.c:693 0xfffffc0100cbc70
<...more frames...>
Fixes: bb9632320ba7 ("PCI: dw: rockchip: Support rockchip_dw_pcie_pm_ctrl_for_user")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I2bff726b30c0c5fcaef62aa5cc80548aedbb4505
1. RK3566/RK3568/RK3588 VOP different VPs share one overlay logic,
so need use ovl lock to make sure they're mutually exclusive, Except
this three platform, other VOP each VP have independent overlay logic.
2. RK3528 need to reset the p2i_en bit when POST_BUF_EMPTY at
post_buf_empty_work_event(), the vop2_cfg_done() must exclusive with
userspace commit new frame.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I84feb978e00a6c5d32266cd3946610e0cc09868b
The output_type may changed after DP encoder bound to CRTC. For
example, when performing modeset, calling vop2_crtc_atomic_disable()
will clear the output_type to zero. When drm_mode_getconnector() is
called again, since the encoder has already been bound to the CRTC,
the output_type will not be set and will remain zero. It can lead to
the vop2_crtc_mode_valid() being unable to retrieve the correct
output_type.
This patch set output_type in dw_dp_encoder_mode_valid(), regardless
of whether encoder is already bound to a CRTC.
Change-Id: I1888d4cc44604072bbf0cbe67a0d21fa8303b7b0
Signed-off-by: chaoyi.chen <chaoyi.chen@rock-chips.com>
According to the include/drm/drm_bridge.h, the following functions
are mandatory in atomic mode:
&drm_bridge_funcs.atomic_reset()
&drm_bridge_funcs.atomic_duplicate_state()
&drm_bridge_funcs.atomic_destroy_state()
For some bridge drivers that have not supported atomic mode yet:
drivers/gpu/drm/bridge/sii902x.c
drivers/gpu/drm/bridge/rk630-tve.c
......
The drm_atomic_get_bridge_state() should not be called to get the
bridge state by the global atomic state. Without this patch, the null
pointer exception will occur.
Fixes: 3558926745 ("drm/rockchip: logo: call drm_atomic_bridge_chain_check() bridge in mode fixup")
Change-Id: I68c953db21a95bf5454fc47c65958dee9d13a8ce
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
RK3518 is a Soc base on Rockchip RK3528, the cpu freq
is lower than RK3528 and remove PCIE/RGMII supported.
Change-Id: I9334959b598ece349dfce7e2b922cf91562c61ac
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
When applptr exceeds buffer boundaries, the calculated offset
becomes misaligned with the actual buffer position, causing
loopback capture data loss.
This patch fix it by applying boundary checks during applptr updates.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I7c6497a9aa7e12e9b3e1c14dcc6de74bbc1515e2
This code has been removed in the upstream version, but it's left
in the internal project.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I4d41bfa646df698d24d38c98244529f8ea53f47e
According to deepseek suggestion, fix the following potential issues:
1. drm_gem_object_init() does not check the return value,
causing memory leak;
2. The alloc_kmap flag maybe overwritten by an error in
rockchip_gem_create_with_handle();
3. Resource leak exists in rockchip_gem_prime_import_sg_table();
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I998feace191784638bf68bf53f57ff74c4ecf6dd
The relationships between the main window and the splice window are:
Main | Splice
Cluster0 | Cluster1
Cluster2 | Cluster3
Esmart0 | Esmart1
Esmart2 | Esmart3
The VP0 and VP1 should be used in combination when the display mode is
over 4k. The main window should attach to the VP0, while the splice
window should attach to the other.
Without this patch, the default plane_mask may not meet the above
requirement when the plane_mask is not assigned in DTS.
Change-Id: Ia676f519ce26d579b1066841715fe8678dc15852
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
There is no need to do dwc2_core_init() for Rockchip SOCs if the
logic is not powered off after system suspend. If the logic is
powered off after system suspend, we will reinitialize the core
in dwc2_resume() function.
Change-Id: Ibe6d0e81e5a39feca528c838c187cfe8c31269f5
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
