Print an error message when a DMA channel cannot be allocated.
Change-Id: I93a96851ac12c5ea66b2fb053033aa4260c2178a
Signed-off-by: Mike Corrigan <michael.corrigan@motorola.com>
akiphie points out that a.out core-dumps have that odd task struct
dumping that was never used and was never really a good idea (it goes
back into the mists of history, probably the original core-dumping
code). Just remove it.
Also do the access_ok() check on dump_write(). It probably doesn't
matter (since normal filesystems all seem to do it anyway), but he
points out that it's normally done by the VFS layer, so ...
[ I suspect that we should possibly do "vfs_write()" instead of
calling ->write directly. That also does the whole fsnotify and write
statistics thing, which may or may not be a good idea. ]
And just to be anal, do this all for the x86-64 32-bit a.out emulation
code too, even though it's not enabled (and won't currently even
compile)
Reported-by: akiphie <akiphie@lavabit.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
-- Ignore kfifo thresholds on recording and playback and adjust the delays.
-- Take out the code from TEGRA_AUDIO_IN_STOP into a separate function
stop_recording_nosync()
-- Rename stop_recording() to wait_for_recording_to_stop().
-- add ioctl(TEGRA_AUDIO_OUT_FLUSH), which blocks the caller until the output
fifo is drained. While the caller is blocked, pending write() calls will
return immediately with whatever data they had managed to queue up.
-- removed ioctl(TEGRA_AUDIO_OUT_PRELOAD_FIFO)
-- since TEGRA_AUDIO_OUT_FLUSH and TEGRA_AUDIO_IN_STOP act similarly, moved
audio_driver_state::recording_cancelled to audio_stream::stop and changed
the code accordingly. Renamed functions wait_for_recording_to_stop() and
stop_recording_nosync() to wait_till_stopped() and request_stop_nosync()
since they handle both playback and recording.
-- print errors on close() if wakelocks are still held
-- Call request_stop_nosync() on close() of a recording file handle
-- Do not use struct audio_stream::active for playback streams. Instead,
where applicable, use kfifo_len(). As a consequence, playback kfifo
underruns are no longer reported. These were bogus anyway, as we really
need the DMA engine to tell us if there are underruns.
-- Because of above item, had to rework tx_fifo_atn_store(),
rx_fifo_atn_store(), and __attr_fifo_atn_write().
-- Set struct audio_stream::active for a recording stream to true when a
recording starts, and set it to false when recording get stopped. Do not
set/clear it within the body of read(), because just being within read()
does not mean that recording is in progress.
-- In tegra_audio_read(), check for stop == true before calling
start_recording_if_necessary(); this makes sure that if a user calls read()
after calling ioctl(TEGRA_AUDIO_IN_STOP), recording will not resume unless
ioctl(TEGRA_AUDIO_IN_START) gets called, or the file is closed and
re-opened.
-- Fixed TEGRA_AUDIO_IN_START
-- In PIO mode, enabled FIFOs before enabling interrupts as specified in the
TRM.
-- Added missing break in tegra_audio_ioctl().
-- Silenced some debug spew
Signed-off-by: Iliyan Malchev <malchev@google.com>
* master.kernel.org:/home/rmk/linux-2.6-arm:
ARM: relax ioremap prohibition (309caa9) for -final and -stable
ARM: 6440/1: ep93xx: DMA: fix channel_disable
cpuimx27: fix i2c bus selection
cpuimx27: fix compile when ULPI is selected
ARM: 6435/1: Fix HWCAP_TLS flag for ARM11MPCore/Cortex-A9
ARM: 6436/1: AT91: Fix power-saving in idle-mode on 926T processors
ARM: fix section mismatch warnings in Versatile Express
ARM: 6412/1: kprobes-decode: add support for MOVW instruction
ARM: 6419/1: mmu: Fix MT_MEMORY and MT_MEMORY_NONCACHED pte flags
ARM: 6416/1: errata: faulty hazard checking in the Store Buffer may lead to data corruption
* 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6:
omap: iommu-load cam register before flushing the entry
* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
x86, numa: For each node, register the memory blocks actually used
x86, AMD, MCE thresholding: Fix the MCi_MISCj iteration order
x86, mce, therm_throt.c: Fix missing curly braces in error handling logic
register the tegradc0, tegradc1, grhost, pwm-backlight and carveout
devices
Change-Id: Ia61c0632470e571cc57279dc3b197ccd1fca80f0
Signed-off-by: Gary King <gking@nvidia.com>
when allocating uncached pages, the outer cache should be flushed;
the end address should be specified in bytes, not in pages.
Change-Id: I3fe036f4f7e10e009f96567e3afeeef6ea603240
Signed-off-by: Gary King <gking@nvidia.com>
... but produce a big warning about the problem as encouragement
for people to fix their drivers.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
When channel_disable() is called, it disables per channel interrupts and
waits until channels state becomes STATE_STALL, and then disables the
channel. Now, if the DMA transfer is disabled while the channel is in
STATE_NEXT we will not wait anything and disable the channel immediately.
This seems to cause weird data corruption for example in audio transfers.
Fix is to wait while we are in STATE_NEXT or STATE_ON and only then
disable the channel.
Signed-off-by: Mika Westerberg <mika.westerberg@iki.fi>
Acked-by: Ryan Mallon <ryan@bluewatersys.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russ reported SGI UV is broken recently. He said:
| The SRAT table shows that memory range is spread over two nodes.
|
| SRAT: Node 0 PXM 0 100000000-800000000
| SRAT: Node 1 PXM 1 800000000-1000000000
| SRAT: Node 0 PXM 0 1000000000-1080000000
|
|Previously, the kernel early_node_map[] would show three entries
|with the proper node.
|
|[ 0.000000] 0: 0x00100000 -> 0x00800000
|[ 0.000000] 1: 0x00800000 -> 0x01000000
|[ 0.000000] 0: 0x01000000 -> 0x01080000
|
|The problem is recent community kernel early_node_map[] shows
|only two entries with the node 0 entry overlapping the node 1
|entry.
|
| 0: 0x00100000 -> 0x01080000
| 1: 0x00800000 -> 0x01000000
After looking at the changelog, Found out that it has been broken for a while by
following commit
|commit 8716273cae
|Author: David Rientjes <rientjes@google.com>
|Date: Fri Sep 25 15:20:04 2009 -0700
|
| x86: Export srat physical topology
Before that commit, register_active_regions() is called for every SRAT memory
entry right away.
Use nodememblk_range[] instead of nodes[] in order to make sure we
capture the actual memory blocks registered with each node. nodes[]
contains an extended range which spans all memory regions associated
with a node, but that does not mean that all the memory in between are
included.
Reported-by: Russ Anderson <rja@sgi.com>
Tested-by: Russ Anderson <rja@sgi.com>
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
LKML-Reference: <4CB27BDF.5000800@kernel.org>
Acked-by: David Rientjes <rientjes@google.com>
Cc: <stable@kernel.org> 2.6.33 .34 .35 .36
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
The VMCB is reset whenever we receive a startup IPI, so Linux is setting
TSC back to zero happens very late in the boot process and destabilizing
the TSC. Instead, just set TSC to zero once at VCPU creation time.
Why the separate patch? So git-bisect is your friend.
Signed-off-by: Zachary Amsden <zamsden@redhat.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
On reset, VMCB TSC should be set to zero. Instead, code was setting
tsc_offset to zero, which passes through the underlying TSC.
Signed-off-by: Zachary Amsden <zamsden@redhat.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
This fixes possible cases of not collecting valid error info in
the MCE error thresholding groups on F10h hardware.
The current code contains a subtle problem of checking only the
Valid bit of MSR0000_0413 (which is MC4_MISC0 - DRAM
thresholding group) in its first iteration and breaking out if
the bit is cleared.
But (!), this MSR contains an offset value, BlkPtr[31:24], which
points to the remaining MSRs in this thresholding group which
might contain valid information too. But if we bail out only
after we checked the valid bit in the first MSR and not the
block pointer too, we miss that other information.
The thing is, MC4_MISC0[BlkPtr] is not predicated on
MCi_STATUS[MiscV] or MC4_MISC0[Valid] and should be checked
prior to iterating over the MCI_MISCj thresholding group,
irrespective of the MC4_MISC0[Valid] setting.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Cc: <stable@kernel.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
* 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: SAMSUNG: Add a workaround for get_clock() for serial driver
ARM: S5P: Bug fix on errors of build with CONFIG_PREEMPT_NONE
ARM: SAMSUNG: Fix build warnings because of unused codes
Define an _addr_lsb field in the mips and ia64 siginfo_ts, following
the asm-generic version. This just puts the field over padding.
This fixes a compilation problem introduced with a337fda.
Cc: ralf@linux-mips.org
Cc: tony.luck@intel.com
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
includes changes by:
Antti Hatala <ahatala@nvidia.com> (1)
Gary King <gking@nvidia.com> (1)
Erik Gilling <konkers@android.com> (2)
Antti Hatala <ahatala@nvidia.com>
video: tegra: dc: use nvhost driver for host1x power management
Gary King <gking@nvidia.com>
video: tegra: fb: add ioctl to flip dc windows to nvmap handles
Erik Gilling <konkers@android.com>
video: tegra: dc: increment syncpoints following window flips
video: tegra: drain syncpt waits on display disable
Original commit messages:
**
video: tegra: dc: use nvhost driver for host1x power management
Incrementing the frame done syncpoint value from the display interrupt
requires that the host module is powered on. As the syncpoint state is
saved and restored automatically by the host driver a cpu increment of
a syncpoint in the powered down state will be lost.
Also adds checks for host module being powered.
**
video: tegra: fb: add ioctl to flip dc windows to nvmap handles
tegra user-space graphics drivers may allocate framebuffers using
nvmap rather than rendering to the common framebuffer, this may
be done to support deeper buffer pipelining, color formats
and pixel layouts other than the initial bootup framebuffer,
etc.
to use this ioctl, a caller must first specify an nvmap fd
which is already open in the calling process so that the
subsequent flip ioctls may be properly validated. flips are performed
asynchronously, with flip completion notifications provided back to
the caller via the host1x syncpoint mechanism
based on earlier changes made by Antti Hatala <ahatala@nvidia.com>
and Erik Gilling <konkers@android.com>
Change-Id: I4e8a8bb92085a485d65fd87d89112b2969ee37ff
Signed-off-by: Gary King <gking@nvidia.com>
the graphics and display hardware on tegra SoCs is accessed
through a command DMA front-end called host1x
host driver clients place commands into memory objects called
streams, and submit a stream on one of 8 channels: the assignment
of streams-to-channels depends on the hardware module(s) programmed
by the stream: for example, all streams which program the 3D
hardware are submitted on channel 1.
the host1x hardware includes two synchronization primitives to
allow command streams to synchronize access to memory or to
hardware engines shared across channels (e.g. the 2D blitter):
sync points and module mutexes. both primitives can also be
used to synchronize with the CPU.
the host1x driver performs power management for all modules
behind the host block: once a module is idle (i.e., the
last stream which accesses it has completed, indicated by
a syncpoint) and has remained idle for an extended period
of time, the module's clock (and power gate island, if the
module is uniquely power-gated) is disabled, and will be
automatically re-enabled when a new stream is submitted for
that module.
includes channel debugging support originally implemented
by Erik Gilling <konkers@google.com>
Original Author: Antti Hatala <ahatala@nvidia.com>
Signed-off-by: Gary King <gking@nvidia.com>
Change-Id: Idf0ecc8e7710f3839903a9fbfbe5650990a96b2c
framebuffers will generally not be exactly width * bpp / 8 bytes wide;
on tegra, linearly-addressed framebuffers will generally be rounded
up so that the stride is a multiple of 16B (so that they are compatible
with rendering from the hardware engines), and tiled framebuffers
will be a multiple of the tile width (64B).
add a utility function to tegra_dc to compute the correct stride
given a width, bpp and pixel layout, and use this in set_par.
Change-Id: I803a55b49c12476f20d5644707899c3fe1336c2d
Signed-off-by: Gary King <gking@nvidia.com>
nvmap provides an interface for user- and kernel-space clients to
allocate and access memory "handles" which can be pinned to enable
the memory to be shared with DMA devices on the system, and may
also be mapped (using caller-specified cache attributes) so that
they are directly accessible by the CPU.
the memory handle object gives clients a common API to allocate from
multiple types of memory: platform-reserved physically contiguous
"carveout" memory, physically contiguous (order > 0) OS pages,
or physically discontiguous order-0 OS pages that can be remapped
into a contiguous region of the DMA device's virtual address space
through the tegra IOVMM subsystem.
unpinned and unmapped memory handles are relocatable at run-time
by the nvmap system. handles may also be shared between multiple
clients, allowing (for example) a window manager and its client
applications to directly share framebuffers
Change-Id: Ie8ead17fe7ab64f1c27d922b1b494f2487a478b6
Signed-off-by: Gary King <gking@nvidia.com>
For streaming-style operations (e.g., software rendering of graphics
surfaces shared with non-coherent DMA devices), the cost of performing
L2 cache maintenance can exceed the benefit of having the larger cache
(this is particularly true for OUTER_CACHE configurations like the ARM
PL2x0).
This change uses the currently-unused mapping 5 (TEX[0]=1, C=0, B=1)
in the tex remapping tables as an inner-writeback-write-allocate, outer
non-cacheable memory type, so that this mapping will be available to
clients which will benefit from the reduced L2 maintenance.
Change-Id: Iaec3314a304eab2215100d991b1e880b676ac906
Signed-off-by: Gary King <gking@nvidia.com>
mirror the change to v7 common startup in the tegra-specific
LP2 and hotplug statup routines
Change-Id: I0552eba951dbfc168e37e59b41394d31fab30256
Signed-off-by: Gary King <gking@nvidia.com>
the "streaming" mode optimization which skips cacheline allocation
for fully-dirty lines is frequently defeated when coherent processors
perfom stores simultaneously
this results in cachelines being allocated in SMP which are not
allocated when run in uniprocessor, resulting in a significant
reduction in aggregate write bandwidth. for example, on Tegra 2
systems with 300MHz DDR main memory, running memset over a large
buffer (i.e., L2 miss) on a single processor will achieve ~2GB/sec
of write bandwidth, but if the same operation is run in parallel on
both CPUs, the aggregate write bandwidth is just 500MB/sec
changing the cache allocation policy to read-allocate reduces some
of this performance loss on SMP systems.
Change-Id: Ice47ab0a15f2490b7e9a007b4b37800566ed7be1
Signed-off-by: Gary King <gking@nvidia.com>
the memory remapping (NMRR) registers were configured differently
by the SMP and LP2 startup code from the standard kernel.
temporarily reverting the inner-writeback change for now.
Change-Id: Ib9c4fc75580d1cc705a5dd83377c0703669bcabc
Signed-off-by: Gary King <gking@nvidia.com>
ARM CPUs with speculative prefetching have undefined behaviors when the
same physical page is mapped to two different virtual addresses with
conflicting cache attributes.
since many recent systems include IOMMU functionality (i.e., remapping
of discontiguous physical pages into a virtually-contiguous address
range for I/O devices), it is desirable to support allocating any
available OS memory for use by the I/O devices. however, since many
systems do not support cache coherency between the CPU and DMA devices,
these devices are left with using DMA-coherent allocations from the OS
(which severely limits the benefit of an IOMMU) or performing cache
maintenance (which can be a severe performance loss, particularly on
systems with outer caches, compared to using DMA-coherent memory).
this change adds an API for allocating pages from the OS with specific
cache maintenance properties and ensures that the kernel's mapping
of the page reflects the desired cache attributes, in line with the
ARMv7 architectural requirements
Change-Id: If0bd3cfe339b9a9b10fd6d45a748cd5e65931cf0
Signed-off-by: Gary King <gking@nvidia.com>
add a kernel configuration to map the kernel's lowmem pages using PTE
mappings, rather than the default behavior of 1MiB section mappings.
on ARMv7 processors, to support allocating pages with DMA-coherent
cache attributes, the cache attributes specified in the kernel's
mapping must match cache attributes specified for other mappings;
to ensure that this is the case, the kernel's attributes must be
specified on a per-page basis.
to avoid problems caused by the init_mm page table allocations exceeding
the available initial memory, when this config is enabled lowmem is
initially mapped using sections (matches current behavior), then remapped
using pages after bootmem is initialized
Change-Id: I8a6feba1d6806d007e17d9d4616525b0446c0fb1
Signed-off-by: Gary King <gking@nvidia.com>
Added an ioctl to set the bit format for I2S between "DSP"/"PCM" mode and
normal mode (set by board file)
Signed-off-by: Iliyan Malchev <malchev@google.com>
Recent clean of i.MX devices registration changed the i2C bus number
selected for our platform (Freescale start peripheral ID at 1, kernel
now start it at 0 so i.MX27's i2c 1 is kernel's i2c 0).
Without this fix, i2c is unusable on this platform.
Signed-off-by: Eric Bénard <eric@eukrea.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
without this patch we get :
arch/arm/mach-imx/built-in.o: In function `eukrea_cpuimx27_init':
eukrea_mbimx27-baseboard.c:(.init.text+0x44c): undefined reference to `mxc_ulpi_access_ops'
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Commit 14eff18126 added proper
detection for ARM11MPCore/Cortex-A9 instead of detecting them
as ARMv7. However, it was missing the HWCAP_TLS flags.
HWCAP_TLS is needed if support for earlier ARMv6 is compiled
into the same kernel. Without HWCAP_TLS flags the userspace
won't work unless nosmp is specified:
Kernel panic - not syncing: Attempted to kill init!
CPU0: stopping
<c005d5e4>] (unwind_backtrace+0x0/0xec) from [<c004c2f8>] (do_IPI+0xfc/0x184)
<c004c2f8>] (do_IPI+0xfc/0x184) from [<c03f25bc>] (__irq_svc+0x9c/0x160)
Exception stack(0xc0565f80 to 0xc0565fc8)
5f80: 00000001 c05772a0 00000000 00003a61 c0564000 c05cf500 c003603c c0578600
5fa0: 80033ef0 410fc091 0000001f 00000000 00000000 c0565fc8 c00b91f8 c0057cb4
5fc0: 20000013 ffffffff
[<c03f25bc>] (__irq_svc+0x9c/0x160) from [<c0057cb4>] (default_idle+0x30/0x38)
[<c0057cb4>] (default_idle+0x30/0x38) from [<c005829c>] (cpu_idle+0x9c/0xf8)
[<c005829c>] (cpu_idle+0x9c/0xf8) from [<c0008d48>] (start_kernel+0x2a4/0x300)
[<c0008d48>] (start_kernel+0x2a4/0x300) from [<80008084>] (0x80008084)
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
According to Atmel, their 926T processors (AT91 post RM9200) requires
'Wait for Interrupt' mode be entered right after disabling the processor clock
in order to minimise current consumption when idle, so do both provided we're
not running on a 920T (an RM9200).
Furthermore, get rid of the #ifndef CONFIG_DEBUG_KERNEL, since arch_idle()
can be turned off completely with the kernel parameter 'nohlt'.
Cc: Andrew Victor <avictor.za@gmail.com>
Signed-off-by: Anders Larsen <al@alarsen.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Serial drivers call get_clock() very early, before platform bus
has been set up, this requires a special check to let them get
a proper clock. Without this patch, a serial console is broken
on S5PV310 and S5PC210 boards.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
[kgene.kim@samsung.com: fix coding-style]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Cc: Ben Dooks <ben-linux@fluff.org>
