Refer to lowlevel mechanism of dwc2, amend the PHY operation
process in case of unbalance for power on and off as well.
This patch fix unbalanced phy power management if otg cable
plug in between the completion of dwc2 probe and udc_start.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: Ic0c2811ed84f8f46e99e03eff44c9d20a791e05f
The usb phys need to be controlled dynamically on some Rockchip SoCs.
So set the new HCD flag which prevents USB core from trying to manage
our phys.
Change-Id: I2d1197f42fe49bc4e454954481f344256fddb557
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The dwc2 programming guide section 3.5 'Halting a Channel'
says that the application can disable any channel by
programming the HCCHARn register with the HCCHARn.ChDis
and HCCHARn.ChEna bits set to 1'b1. This enables the
dwc_otg host to flush the posted requests (if any) and
generates a Channel Halted interrupt.
But it also requires that channel disable must not be
programmed for non-split periodic channels. At the end
of the next uframe/frame (in the worst case), the core
generates a channel halted and disables the channel
automatically.
If we disable non-spilt periodic channels to halt the
channels, it will easily to cause data transfer fail.
A typical case is take photo with usb camera or close
usb camera, Specifically, the observed order is:
1. uvc driver calls usb_kill_urb
2. usb_kill_urb calls urb_dequeue to cancel urb
3. urb_dequeue call dwc_otg_hc_halt to disable
non-spilt periodic channels
4. usb core doesn't halt the non-spilt periodic
channels immediately, and the application
reallocates the channels for other transactions
without waiting for the HCINTn.ChHltd interrupt.
5. uvc driver calls usb_set_interface to start
control transfer, and gets a channel which used
for non-spilt periodic transfer before. The core
generates a channel halted and disables the channel
automatically. This cause control transfer fail.
Change-Id: I95424a99b77b552396a9fb95a5058258270ed4c2
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The commit e6f2f6d63e ("usb: dwc2: power on/off phy for
otg mode") aimed to control phy power for otg mode, but
it also introduced a new problem, so we fix it.
This patch keep phy power on for otg if current mode is
host during dwc2 probe, otherwise the enumeration will
fail with the following error log:
Cannot enable. Maybe the USB cable is bad?
Cannot enable. Maybe the USB cable is bad?
attempt power cycle
Cannot enable. Maybe the USB cable is bad?
Cannot enable. Maybe the USB cable is bad?
unable to enumerate USB device
Change-Id: I17a4cab6f0337fdc0923989aea8613bfbe1a9e9b
Fixes: e6f2f6d63e ("usb: dwc2: power on/off phy for otg mode")
Signed-off-by: Feng Mingli <fml@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The frame_overrun flag is used to indicates
SOF number (current_frame) overrun in DSTS
and the target_frame over DSTS_SOFFN_LIMIT.
Clear the frame_overrun flag only if target_frame
below DSTS_SOFFN_LIMIT and current_frame less
than target_frame.
Change-Id: I91cf9001324a9bbbcc4bc28b335695d607fb69d4
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Adds pm_runtime support for dwc2, so that power domain is
enabled only when there is a transaction going on to help
save power.
Change-Id: I318552774d20eeaed521ff179f99b2551ee24183
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The operation mode of controller will change to peripheral when
resume if PD is power off during suspend, current code disconnect
hcd and set lx state to L3 in this case to make sure the controller
will be reinit in device mode, but that's not enough, the op_state
is still host which is change when init or ID change interrupt
occur. If the ID change happened after suspend the driver would
miss the interrupt, so when the application call the pullup function
to stop gadget and start again to change to another function, the
disconnect gadget operation can't be done and the gadget restart
directly. This will result in NULL point when gadget work. This
patch set op_state to OTG_STATE_B_PERIPHERAL when resume in this
case.
Change-Id: Ifbafb7fae43d634cfa879c9a066d1e114db4196e
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The controller will reset and run into error state if turn
off power when suspend in host mode. This patch stop hcd to
make the controller into L3 state to make sure that the
controller and driver state will reset when resume.
Change-Id: If66bc1a249e919f440ecde0c66f18dabde0b2e62
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The commit dc71e51944 ("usb: dwc2: make otg manage lowlevel
hw on its own") aimed to control the clk and phy power for
otg mode, but it also introduced lost of new problems, so we
revert it.
This patch only controls phy power for otg mode, it can fix
the dwc2 udc start fail issue with the following error log:
dwc2_hsotg_init_fifo: timeout flushing fifos (GRSTCTL=80000430)
dwc2_core_reset() HANG! Soft Reset GRSTCTL=80000001
bound driver configfs-gadget
dwc2_core_reset() HANG! Soft Reset GRSTCTL=80000001
Change-Id: Id6996aecab7f0aaaf12530b7a377144e23ef1667
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
When handle disconnect of the hcd during bus_suspend, hcd
needs to resume its root hub, otherwise the root hub will
not disconnect the existing devices under its port.
This issue always happens when connecting with usb devices
which support auto-suspend function (e.g. usb hub).
(am from https://patchwork.kernel.org/patch/9751469/)
Change-Id: I663fdea73f36e89130d9a250612363968cbff941
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Originally, dwc2 just handle one otg clock, however, it may have
two or more clock need to manage for some vendor SoCs, so this
reworks to use bulk clock APIs.
Change-Id: I661297ef908d9eace2215205018fa94d12cea128
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The DWC2 driver auto detects the hardware and enable
the gadget descriptor DMA if the DWC2 IP supports it.
However, the gadget descriptor DMA has some unexpected
compatibility issues, so we use buffer DMA instead of
desc DMA.
Change-Id: I1fed77f7d9bec1e0916b44d80813fb6248d461f0
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
LPM feature of DWC2 module integrated in Rockchip SoCs doesn't work
properly or needs some additional handling, so disable it for now.
Without disabling LPM feature, the USB ADB communication fail with
the following error log:
dwc2 ff580000.usb: new address 27
dwc2 ff580000.usb: Failed to exit L1 sleep state in 200us.
dwc2 ff580000.usb: dwc2_hsotg_send_reply: cannot queue req
dwc2 ff580000.usb: dwc2_hsotg_process_req_status: failed to send reply
dwc2 ff580000.usb: dwc2_hsotg_enqueue_setup: failed queue (-11)
dwc2 ff580000.usb: Failed to exit L1 sleep state in 200us.
Change-Id: I4e2b243fba2f1536c39f313232433cfd295113d6
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
usage:
(1) force host mode
echo 1 > /sys/devices/platform/ff770000.syscon/ff770000.syscon:usbphy/phy/phy-ff770000.syscon:usbphy.2/otg_mode
(2) force device mode
echo 2 > /sys/devices/platform/ff770000.syscon/ff770000.syscon:usbphy/phy/phy-ff770000.syscon:usbphy.2/otg_mode
Change-Id: I44fa1461076e6c0cd8aba1e2e444004cfb3f5271
Signed-off-by: Wang Jie <dave.wang@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
We found that the system was blocked in EHCI when perform suspend or
reboot on RK3288 platform, the root cause is that EHCI (auto) suspend
causes the corresponding usb-phy into suspend mode which would power
down the inner PLL blocks in usb-phy if the COMMONONN is set to 1'b1.
The PLL output clocks contained CLK480M, CLK12MOHCI, CLK48MOHCI, PHYCLOCK0
and so on, these clocks are not only supplied for EHCI and OHCI, but also
supplied for GPU and other external modules, so setting COMMONONN to 1'b0
to keep the inner PLL blocks in usb-phy always powered.
Change-Id: Ifb7f3d233cf72155aa54d20b15a62b683944a526
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This fixes "submode" parameter for PHY set_mode() callback function.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: Ia42b77e22914b995c8cea5910ae3a364269d9cfb
If the OTG work in Host mode, delay power off phy in OTG_STATE_B_IDLE
state when unplug OTG cable, this can fix the xHCI deregistered error
with the following log on RK356x platforms:
[ 16.856295] xhci-hcd xhci-hcd.5.auto: remove, state 4
[ 16.856340] usb usb8: USB disconnect, device number 1
[ 16.857778] xhci-hcd xhci-hcd.5.auto: USB bus 8 deregistered
[ 16.858108] xhci-hcd xhci-hcd.5.auto: remove, state 4
[ 16.858146] usb usb7: USB disconnect, device number 1
[ 16.878109] xhci-hcd xhci-hcd.5.auto: Host halt failed, -110
[ 16.878151] xhci-hcd xhci-hcd.5.auto: Host controller not halted, aborting reset.
[ 16.878853] xhci-hcd xhci-hcd.5.auto: USB bus 7 deregistered
Change-Id: I4467afdd3fe20839a9ec967624868ce3773e048c
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch adds a new vbus_detect helper function to control
the vbus voltage level detection for rk3568 otg port. And
fix the issue that the bvalid irq status and id irq status
are not handled in the rockchip_usb2phy_irq() for otg host
mode when force mode via the sys interface "otg_mode".
Change-Id: I75a102034e8dd3ad47de67da4e5120e28564368e
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
RK3568 has two USB 2.0 PHYs, and each PHY has two ports, the
OTG port of PHY0 support OTG mode with charging detection
function, they are similar to previous Rockchip SoCs.
However, there are three different designs for RK3568 USB 2.0 PHY.
1. RK3568 uses independent USB GRF module for each USB 2.0 PHY.
2. RK3568 accesses the registers of USB 2.0 PHY IP directly by APB.
3. The two ports of USB 2.0 PHY share one interrupt.
Change-Id: Id05718e25a20abdf9a4cb353b0fb94f0cb8b2d75
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This adds "rockchip,rk3568-usb2phy" compatible property.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I18673c75cdb7c5eea04eb347b4114f0b8304762a
Since RK356x, the USB PHY GRF adds new registers to select
bvalid from USB PHY or GRF. And in RK356x Maskrom USB driver,
it selects the bvalid from GRF and sets the bvalid value to 1,
it aims to improve the compatibility of various USB circuits
for Maskrom USB. However, the charger detection and USB PHY
power consumption control depends on the bvalid of USB PHY.
So this patch selects bvalid from USB PHY for otg port.
Change-Id: I3fc9faf06f30e0a3390bc4fd40c732fb856131f8
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
In order to switch the drd mode of the dwc3 controller by software, we
add these registers in the driver.
Change-Id: Ice5009631f491915ca78b5310cc9c623269bff41
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Some chips like rk3328 not support wakeup-config in dts,
So we should set wakeup IRQ enable in driver if we need
new wakeup source.
Change-Id: I735eee54bb4943b8c85a9a477f1cf9d255fc4312
Signed-off-by: Zain Wang <wzz@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Add common helper function rockchip_usb2phy_port_irq_init() for
both otg port and host port to init their own irqs. It can help
to reduce redundant code, and also fix a issue that the id irq
isn't enabled for otg port if the vbus_always_on flag is true.
This patch introduces a combined irq for some inno usb2 phys
which combined the irqs of otg port and host port. We will used
it for RK3568 later.
Change-Id: Ifa74ec72e2b9d4ed62ee69e916b8ab2e8ae665b3
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Adds pm_runtime support for some rockchip SoCs (e.g. rk3399)
which support power domain for USB 2.0 PHY.
Change-Id: I4c78075c884b3baf6d709e08e3464b214524d685
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Prevent the system from entering suspend when usb cable is connecetd.
Change-Id: I50c4a09d9142ebeb2d4e2a0ab2df59f98ef99737
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
RK1808 SoC has an usb 2.0 comb phy with one otg-port and one
host-port. This patch adds port configurations for them.
Change-Id: Id4d117929ec0e327c8f2cc1a06d4caaa2d584f06
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
We find an usb phy 480MHz clk prepare fail issue on PX30/RK3326
platforms with RK819 PMIC. On PX30/RK3326 platforms, we set the
usb480m clk to critical because GPU 480M is from usb480m and the
source clocks should be always on. And the usb phy 480MHz clk is
parent of usb480m clk, so the clk framework will prepare the usb
phy 480MHz clk when register it.
This logic works well if the usb phy probe only once. But if the
usb phy needs to probe twice or more because of some reasons (e.g.
fail to get vbus regulator from RK819), the usb phy 480MHz clk will
be unregistered and registered again, however, the clk framework
doesn't prepare the usb phy 480MHz clk except the first time register
operation. So we move the 480MHz clk register to the end of probe,
and make sure only register it once.
Change-Id: If69378b49035746a7c0107c6a363c4d91dfc15e5
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Open pre-emphasize in non-chirp state for rk3228 USB
PHY0 otg port to increase HS slew rate.
Change-Id: Ia565746286a750a251619a83cbbead99c0ddecbd
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Make u2phy enter low power mode when suspend. If config the DT of
u2phy port with "rockchip,low-power-mode" property, the port will
be config to lower power state when suspend.
Bvalid irq and linestate irq will be disabled in this mode.
Change-Id: Ie7d40a9a181b0622b1f8d062a741661548cabd59
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This change adds usb-phy support for rk3308 SoC and amend related
phy Documentation.
Change-Id: I953af94fb4d55d79ae1cba624a04fb4b84e019f6
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Due to usb-phy tuning framework is not added in UPSTREAM codes, so
rk3328 tuning is striped in mainline, this commit make a supplement.
Change-Id: Id8103d65951515b9b21baab14f7125420cea78eb
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch uses a fixed-regulator instead of GPIO pin for
usb vbus power. It doesn't fix any issue, but it makes more
sense to convert the GPIO code into a fixed-regulator.
Change-Id: I7196a9cd592dbb3fab3ef8b9e99babc613a42869
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Most of rockchip SoCs USB 2.0 DP/DM can be bypassed to UART,
it's useful for those platforms without UART interface to
print log via USB interface.
For the time being, we just support for rk312x and rk3399 in
this driver. And we will support for more SoCs in the feature.
With this patch, the user still can't use this bypass function.
It needs to add the property "rockchip,bypass-uart" in the DT
as following:
u2phy0_otg: otg-port {
...
rockchip,bypass-uart;
...
};
And it also needs a special USB cable integrated with an USB
to UART chip.
Note: this function can only be used in debug stage.
Change-Id: Icdab516ff7b327f4a98c3b24bbaf953a605f5278
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The rk312x use different config data which incluce control
register address and value. The patch add config data of
rk312x and match table to support rk3128.
Change-Id: Idd9a5c885cf5e291517e56232e77066eb5d97138
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
rk3399 Type-C1 USB 2.0 PHY supports USB BC1.2. This patch
adds registers configuration for Type-C1 USB BC1.2.
With this patch, and set dr_mode of Type-C1 USB to "otg" or
"peripheral" in the DTS, then the Type-C1 USB can detect USB
battery charger.
Change-Id: I2f07ae675cc6066db46e428e6e27045b911a0773
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Let us put phy-port into suspend mode at initialization time for
saving power consumption, and usb controller will resume it during
probe time if needed.
Change-Id: Id3a66af8ff17612d54fbc80db087bf67eaee7726
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This adds support host-port on rk3368 SoC and amend phy Documentation.
Change-Id: I49a2efe37aad8b34505e4dac08336dc4231f4669
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch creates an usb2 phy attribute group and
provides an attribute "otg_mode" for otg port to
force otg mode independently of the voltage of otg
id pin.
In order to implement the force mode function, we can
select otg plug indicator output (AKA iddig) from GRF,
and set GRF USB otg plug indicator to "0" or "1" to
control iddig status.
We only support rk322x/rk3328 to force otg mode for
the time being.
And we need to disable usb auto suspend function if
we want to force otg mode. Add 'usbcore.autosuspend=-1'
in cmdline to disable usb auto suspend.
Usage:
[1] Force host mode
echo host > /sys/devices/platform/<u2phy dev name>/mode
[2] Force peripheral mode
echo peripheral > /sys/devices/platform/<u2phy dev name>/mode
[3] Force otg mode
echo otg > /sys/devices/platform/<u2phy dev name>/mode
Legacy Usage:
[1] Force host mode
echo 1 > /sys/devices/platform/<u2phy dev name>/mode
[2] Force peripheral mode
echo 2 > /sys/devices/platform/<u2phy dev name>/mode
[3] Force otg mode
echo 0 > /sys/devices/platform/<u2phy dev name>/mode
Change-Id: I875b60b0390e3bd9af34b740cba8f5d53e1df752
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
There are some race conditions related to phy power on/off
and otg charger detection work, otg sm work. I can find at
least three race conditions at present.
Race condition[1]:
The first race condition involving phy power on/off which
may be caused by the following case.
Test on rk3399 evaluation board Type-C0, connect to PC usb
port with Type-C cable, then phy power on/off operation may
be done twice because of race condition between phy driver
and usb controller driver.
CPU 0:
- rockchip_usb2phy_bvalid_irq()
- rockchip_usb2phy_otg_sm_work()
- detect connect to PC usb, do phy power on
- rockchip_usb2phy_power_on()
CPU 1:
- dwc3 driver do runtime resume process
- dwc3_runtime_resume()
- dwc3_core_init()
- phy_power_on()
- rockchip_usb2phy_power_on()
Although we use a suspended flag in rockchip_usb2phy_power_on()
to avoid doing the same things twice, but it's not enough to
prevent race condition if phy driver and usb controller driver
access the rockchip_usb2phy_power_on() at the same time. This
race condition may cause clk management unbalanced.
Race condition[2]:
The second race condition related to phy power on/off and otg
charger detection work. We need to keep the usb phy staying in
suspend mode when do usb charger detection. But now it don't
have any protection to prevent the other threads to operate phy
during charger detection.
The problem can also be easily reproduced on rk3399 evaluation
board Type-C0 when connect to PC usb port with Type-C cable.
CPU 0:
- rockchip_chg_detect_work()
- power off phy and start to do charge detection work
CPU 1:
- dwc3 driver do runtime resume process
- dwc3_runtime_resume()
- dwc3_core_init()
- phy_power_on()
- power on phy again
This race condition may cause charger detection and later usb
enumeration abnormally.
Race condition[3]:
The third race condition involving otg sm work. The otg sm
work can be interrupted by bvalid irq, and the bvalid irq
handler rockchip_usb2phy_bvalid_irq() will do otg sm work,
which may cause unknown error.
This patch uses mutex lock to protect the phy operations,
otg charger detection work and otg sm work.
Change-Id: Ic6845a10b3e69fe9ae6cf0b2d4e2beb098232abd
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This adds amend logic of sm work to compatibly support some legacy SoCs,
because _host_utmi_linestate_ and _host_utmi_hostdisconnect_ GRF status
bits which are required for host sm work were not introduced in these
SoCs.
Change-Id: Ib4f499f592618930ac5016a63b7a530674aa6005
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The usb controller may need to disconnect vbus to trigger disconnect
process or connect vbus to trigger connect interrupt by software. But
current code does not realize the interface. This patch add set mode
function in usb2 phy driver, connect vbus in device mode and disconnect
in other mode.
Change-Id: I49b4180af2f47156a3f4d31f4539f3e444f89a62
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The linestate change interrupt may occur during suspend if port is
not connected. This patch pull down dp/dm when suspend.
Change-Id: I31e992727ea63efbda4ecec7ad3af02626eceb44
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
In the case of platform designed in usb2.0 only mode, which
the dwc3 controller connect without fusb302 and type-c phy
does not work, the u2phy need to support hot plug and detect
otg mode, this patch add support of otg function in this mode.
Change-Id: I428a4f6d17d847c6114d124733e62c0a6236b94e
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Add the new extcon EXTCON_USB_VBUS_EN to enable
vbus output.
Change-Id: I83fb75b2a82ad617dc292967bb4917bbfbcb84cb
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
