set port->cap_lanes to 0 when dp connected error last time, and allow
dp go on probing if there is only one fusb302.
Change-Id: I90169f77ac02a94f42da96f20aacfd51b898de09
Signed-off-by: wenping.zhang <wenping.zhang@rock-chips.com>
Enable the SPDIF optical output on rk3288-firefly boards.
Change-Id: I84701df1b193e69673a963045cbd9fb4069e9741
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
rk3288-firefly board needs vcca_33 to be always on.
Change-Id: Iffde1a2857b92d10bf8f306c2257480fdf7f091c
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
add feature of SUPPORT_RK_DISCRETE_VR for discrete vr device in dp,
and add sync code for nanoc vr device.
Change-Id: I5fe1f29ede8ac35f99b62e524bf541a7aaee4307
Signed-off-by: wenping.zhang <wenping.zhang@rock-chips.com>
In dwc3_gadget_suspend(), if fail to stop DWC3 controller,
and return without do __dwc3_gadget_stop(), it will not
disable ep0 and ep1, and the dep->flags stays in the state
DWC3_EP_ENABLED, this will casue gadget connect failed.
A typical case is:
DWC3 works as DRD mode, fist plug in OTG HOST cable and
works as HOST mode, then plug out HOST calbe, after this
operation, it will do runtime supend -> dwc3_gadget_suspend()
-> dwc3_gadget_run_stop() fail -> return without stop gadget,
and then plug in OTG device cable, fail to connect with PC.
Change-Id: I79daff8a9e8175cd13ac57e2abc63d4e5f694b1c
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
This patch adds runtime power management support for rockchip platform.
It depends on extcon notifier to do runtime resume and runtime suspend.
And since the dwc3 core dev is the only child of dwc3 rockchip dev, so
we need to ensure dwc3 core dev enter runtime suspend befer put dwc3
rockchip dev in runtime suspend. And after do runtime resume dwc3 core
dev, the PM core will resume dwc3 rockchip dev prior to dwc3 core dev
resume. With this patch, we can power off USB3 power domain and disable
clocks in runtime suspend.
Change-Id: Ib529889a8603d12dcdce80e9e0716be44c028bd3
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
The opp table can cover the chips whose leakage is between 30mA and 60mA.
Change-Id: I50be3923eb6016cba6309380006ce902d22fe123
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Devfreq will register notify to rkfb, to handle vop during ddr
changing frequency.
Change-Id: I22365597054b2155ef1b9754d6ecac243520b3ee
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
We probably didn't notice this as we still use
evb-rev1 to test our SSD with PCIe on which
the client interrput is broken actually.
Change-Id: I70e2644b9017cc5cd1b7445efb24fa69e22e0901
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
if userspace set car_reversing 1, rk fb will ignore
buffer from hwc.
Change-Id: Ib3bb9a105a8d6b7a2cc0e71c21bf8cc208b4ffd3
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>
For some special hdmi pixclock we should add support for this clock in hdmi phy mpll table.
Add new format SUPPORT_RK_DISCRETE_VR for rockchip discrete vr device,if hdmi device
is rockchip discrete vr device, please set the vic = HDMI_VIDEO_DISCRETE_VR in hdmi timing.
Change-Id: I820f967a84fbb7737cd9e1c2951b89df63863298
Signed-off-by: wenping.zhang <wenping.zhang@rock-chips.com>
Set vsel pin to active to disable DCDC,
Set vsel pin to inactive to enable DCDC.
Change-Id: Ie7d98730e5f59ffe38f0b88388cfb5b852316fe3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Before reboot if the DCDC is disabled,
the DCDC is still disabled after restart.
We have an method to workaround:
Use vsel pin to switch the voltage between value in FAN53555_VSEL0
and FAN53555_VSEL1. If VSEL pin is inactive, the voltage of DCDC
are controlled by FAN53555_VSEL0, when we pull vsel pin to active,
they would be controlled by FAN53555_VSEL1.
In this case, we can set FAN53555_VSEL1 to disable dcdc,
So we can make vsel pin to active to disable dcdc,
VSEL pin is inactive to enable DCDC.
Change-Id: I14c823ed11dc3369044ad2ed0b53a6027acbccd0
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
On vpu2 register separate interrupt bit and enable bit to different
register. When decoder found a buffer empty error which means the input
stream is not enough for one complete frame decoder will not stop
reading input stream buffer until it reach the end of buffer. This will
cause mmu fault on the buffer end.
In order to avoid this case decoder need to clear the enable bit in the
enable register to stop decoder from reading.
Change-Id: I6133aa4611fab03f6545b4775e8ee2320552445f
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
when rga2 use alpha under mmu, it must config src1
mmu addr for src1 channel will read mmu table
Change-Id: I6131a546421a5195bf3ae183f6fc7cb50fb09cfc
Signed-off-by: Shengqin.Zhang <zsq@rock-chips.com>
Signed-off-by: Zhiqin Wei <wzq@rock-chips.com>
This reverts commit 9730348075.
All Rockchip SoCs only have 64 bytes cache line length, so
it is not need this patch, which increase memory consumption.
Change-Id: Idf684189e7f7011562337a70dc7d26c8dceee7a6
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
Calculate current load with busytime / totaltime from status,
also show the current frequency.
Change-Id: Ic310035db9c5478aa3d0b1e526b47c451fe09d23
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
