if userspace set car_reversing 1, rk fb will ignore
buffer from hwc.
Change-Id: Ib3bb9a105a8d6b7a2cc0e71c21bf8cc208b4ffd3
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>
For some special hdmi pixclock we should add support for this clock in hdmi phy mpll table.
Add new format SUPPORT_RK_DISCRETE_VR for rockchip discrete vr device,if hdmi device
is rockchip discrete vr device, please set the vic = HDMI_VIDEO_DISCRETE_VR in hdmi timing.
Change-Id: I820f967a84fbb7737cd9e1c2951b89df63863298
Signed-off-by: wenping.zhang <wenping.zhang@rock-chips.com>
Set vsel pin to active to disable DCDC,
Set vsel pin to inactive to enable DCDC.
Change-Id: Ie7d98730e5f59ffe38f0b88388cfb5b852316fe3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Before reboot if the DCDC is disabled,
the DCDC is still disabled after restart.
We have an method to workaround:
Use vsel pin to switch the voltage between value in FAN53555_VSEL0
and FAN53555_VSEL1. If VSEL pin is inactive, the voltage of DCDC
are controlled by FAN53555_VSEL0, when we pull vsel pin to active,
they would be controlled by FAN53555_VSEL1.
In this case, we can set FAN53555_VSEL1 to disable dcdc,
So we can make vsel pin to active to disable dcdc,
VSEL pin is inactive to enable DCDC.
Change-Id: I14c823ed11dc3369044ad2ed0b53a6027acbccd0
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
On vpu2 register separate interrupt bit and enable bit to different
register. When decoder found a buffer empty error which means the input
stream is not enough for one complete frame decoder will not stop
reading input stream buffer until it reach the end of buffer. This will
cause mmu fault on the buffer end.
In order to avoid this case decoder need to clear the enable bit in the
enable register to stop decoder from reading.
Change-Id: I6133aa4611fab03f6545b4775e8ee2320552445f
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
when rga2 use alpha under mmu, it must config src1
mmu addr for src1 channel will read mmu table
Change-Id: I6131a546421a5195bf3ae183f6fc7cb50fb09cfc
Signed-off-by: Shengqin.Zhang <zsq@rock-chips.com>
Signed-off-by: Zhiqin Wei <wzq@rock-chips.com>
This reverts commit 9730348075.
All Rockchip SoCs only have 64 bytes cache line length, so
it is not need this patch, which increase memory consumption.
Change-Id: Idf684189e7f7011562337a70dc7d26c8dceee7a6
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
Calculate current load with busytime / totaltime from status,
also show the current frequency.
Change-Id: Ic310035db9c5478aa3d0b1e526b47c451fe09d23
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Android healthd try to listen power_supply subsystem uevent,
but which will block system from suspend on big.LITTLE system
because thermal_cooling_device_unregister will called when
cpufreq_exit. So ignore this uevent when suspend.
Change-Id: I35948498916560d5ec75fe561c9e9d588663ad22
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
Set snd_soc_pm_ops for the pm ops to make sure that the ASoC level of PM
operations are going to happen. This is needed to get suspend/resume
working correctly when the audio is using simple-card.
Change-Id: Id0355673bc89456fedd3d035cbfd0f7f8f51d1da
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
(cherry picked from commit 7c3767115a)
To support ddr frequency scaling function, we need
enable dmc and dfi node.
Change-Id: I84ea6bff679365d86937ff10bcdf466ea31901fb
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
The address of wdt0 and wdt1 are swapped, let's fix it.
Change-Id: I715d181b8984a72ad234d4c1389154f15b60738a
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Get opp table from device node for rk3399 dmc table.
Change-Id: I689078d60ebdadf0954b60de70d05bc56a8d6597
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Change-Id: I4cc6bd9218f6fe0ae09d79c23516c6dbdaa59af2
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
This patch adds the documentation for rockchip rk3399 dmc driver.
Change-Id: Icaff8fa2173ded5c64a08e877d32a8eca1a0c3be
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Change-Id: I85efe7f626e636606508fdd171b14275591c0612
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
This patch adds the documentation for rockchip dfi devfreq-event driver.
Change-Id: Ib5704cdef0c7a53abe3afda126cb1a1adba43b3a
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Change-Id: Ib743ffb642fe0c7c0a3b7db14389803595d868b3
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Change-Id: I9e15dd9e01ab1c51a639a6a59391cd5e0de383b7
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Since evb2 couple with ES1, the power consumption is large enough to
shutdown device in some case.
Let's reduce it's support lists to make things simple.
Change-Id: I145aa0c6a21e41b3c8e6ff32fd15839baa15f81e
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Let's disable it as the auto link training of PCIe
take quite long time without add-in card or M.2
devices available.
Change-Id: I4a48a44574b68da75845a6e614a9970bb5d6685b
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Fix them for matching what the new drivers want.
Change-Id: I6ce43379ab9cf3d274b6b414ec014e431db588b7
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Add support for the Rockchip PCIe controller found on RK3399 SoC platform.
Change-Id: Ic924a0defaef195575beba4dfc92c33b6b5bc3e7
[Shawn: manually backport to 4.4 with some minor changes]
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
