In 1-lane mode, the cif module can detect only SOT but not EOT.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: Ie745e3b6fe6d60013efc33bfc6683651c515dc45
There is already dma_sync_sg_xx to replace arch_dma_prep_coherent/__dma_flush_area.
Update driver version to 1.2.14
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I1dd9d6806c9e6d81391796cc3a27bbf5f6129865
The deserializer is a hotpluggable remote device, so move
drm_connector to serializer driver.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I953cf7a3133666e31ad20305f3462175dc5853f2
Fixes: 4f64073a92 ("mfd: MAX96752F: add stream id for each link")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I8a7bbce97363120fadf3bc2d4f27be7d02cc50aa
It can avoid potential build warn/error when CONFIG_DEBUG_FS
is not set. And also fix the following warning:
drivers/phy/rockchip/phy-rockchip-inno-usb3.c:297:5: warning: no previous prototype for ‘rockchip_u3phy_debugfs_init’ [-Wmissing-prototypes]
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ia5f8c0484f2aea53ba6b9eba0b5c8a68b9fc350e
The error code is missing in this code scenario, add the error code
'PTR_ERR(provider)' to the return value ret.
Eliminate the follow smatch warning:
drivers/phy/rockchip/phy-rockchip-inno-usb3.c:937 rockchip_u3phy_probe() warn: missing error code 'ret'
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: If534350cdae1ee09b210c0d475aa2b8673dc7c64
Fix pinctrk conflicts between rkcif_mipi_lvds1 and rkisp
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: I57335c652cde902b6408d7c49cd6f0dab51128a1
In ABB mode, the wr output will calculate the offset output first address
according to the offset of win0, so it is necessary to use the ABC mode
to ensure that the output is to the correct address.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I3daf6e2793b64689df07c62074bc637055883d8a
The most recent situation is that the null pointer exception
is only reported from repeated reboot test on rk3588_EDGE_SDK,
not on rk3588_Linux_SDK or rk3588_Android_SDK.
Change-Id: I1e5ce9eb9fd32c29294e115e6014a8114c896754
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
PD3.0 Spec 6.4.4.3.2 say that only Responder supports 12 or more SVIDs,
the Discover SVIDs Command Shall be executed multiple times until a
Discover SVIDs VDO is returned ending either with a SVID value of
0x0000 in the last part of the last VDO or with a VDO containing two
SVIDs with values of 0x0000.
In the current implementation, if the last VDO does not find that the
Discover SVIDs Command would be executed multiple times even if the
Responder SVIDs are less than 12, and we found some odd dockers just
meet this case. So fix it.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I3bcb68d452af1946557a4781ecc4752b20562b16
Concurrently set the USB role to the USB2 PHY when we received
role_switch set from the TCPM (Type-C Port Manager).
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ie677ee7f5c62b1c26fb38080ce46ea0a6cabbbc7
For Type-C scene, the TCPM notify the USB role to the USB
controller driver. However, the USB2-PHY is imperceptible.
So use submode to get the desired USB role from the USB
controller driver. Later, we can use the phy_set_mode_ext
in the USB controller driver to pass the desired USB role
to USB2-PHY.
With this patch, it can avoid to do battery charger detection
if the Type-C USB role is Host.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I37d3a43d5e0e82e37d45e2e49fb19c4add595b40
"warn: should 'fout_hz << s' be a 64 bit type?"
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I3b842974c2c1709878702c35963df74acd7f4d2f
Change voltage according to logic leakage.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ic9d3fcf7ab3bd2730ec2a7edb3430ffc22f7e92f
The dev_pm_opp_add() can't be used to add opp with multiple voltage
ranges, and there's no need to add new opp, just need adjust opp rate
according to the rate support by DDR.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ic9dd29bedd22d0b7928110c6d0c6483414b48415
It need enable the hdmi phy pll clock function node when the hdmi
phy pll want be used.
For support dynamic switch dclk with hdmi phy pll, the hdmi phy pll
need config in display subsystem node.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I740b6154b37c1e5d9491fafd33c0b6c0c9ffd149
In uboot, a device can't be used as both phy device and clock
device. So It better to register a child device as clock device.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I6d06f3c3b0f0b48741a5c53f51df1766b2cb0740
