1.full/a2/du/du4: check part also
2.auto mode use full gc16 waveform to reduce ghosting
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
Change-Id: I3a2156ccecc5d630b1adb2425d647fb8efb090be
Add CLK_GATE_NO_SET_RATE for gate clks not allowed to support setting
rate.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Iddd1c958661f8ff9217b8781426314b0619367db
The maximum alpha is 255, but after the product of color and alpha
in the blend formula, the final result is >> 8 (/256) instead of
/255, which will introduce errors.
This fix is that when alpha is 0x80~0xff, then +1.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: Ibba964f29a11eb226aa008a0dd5bf89048524b43
Some traditional display devices like use 1024x768p60 resolution, so we
add this mode to default mode when parse edid failed.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ibb67898f8b0cc7b98f988a783f8eb4c28aa18359
Some traditional display devices like use 1024x768p60 resolution,
so we add this mode to default mode when parse edid failed.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I0acd1241d84ae65d415f595d6147fed3da0b2f20
This will used when product use edp2hdmi or edp2vga output.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Idf02a0d1e1bcef579fb3d6117a5e89744bdaac8a
When setting the 16550 serial port baud rate, you need
to configure the UART to loopback mode. After setting
the DLL and DLH, you need to reset the LSR first,
and then configure the MCR to make the UART return
to the normal mode. If you do not reset the LSR
first, an error will occur when the UART RX is still
receiving data.
Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Change-Id: Ia940b278554ef1d4e7a6c4550fe4a4600407a57e
Amend to fix the UAC2 gadget could not be identified on Windows 10 OS.
Fixes: 486bd80e78f4 ("UPSTREAM: usb: f_uac2: adds support for SS and SSP")
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I992af23ab4ac2740a33621d9c3c47368f5135710
This reverts commit 6a1a1cf4e7.
1.Set rk3568 spi node to fall back point
2.Both rk3568 and rv1126's spi is the same design
Change-Id: Ibbb8e4005ad7cd2a6d53eb4c700d657e1f95be7f
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Both rk3568' spi is compatible with rk3036's spi design.
Change-Id: I952beb57c151e77165db781bc17ec782b6bc62a4
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
the sub_dev will be update by list_for_each_entry() and return !NULL
error pointer when no found subdev;
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I8d7db3b66c6c57b986a42cac9ed6eca53b72611e
The current output code only supports connection to drm panels.
Add code to support drm bridge, to support connections to
external connectors.
Change-Id: I775244b7183692f07b74123fa43c8bb958525087
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Validate the cached values of link parameters before
attempting to retrain.
Change-Id: Idf4f8a7c2d85109e05dc7e387f46ddeb55cd0a01
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Split dynamic lane configuration from tcphy_dp_cfg_lane().
Change-Id: Ie4ce3138b30f3f9304daec9a9c582091548c0e60
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
According the CEA-861, HDMI outputs the limited range by default.
Change-Id: I06fc1b92ca15e17fd27f3c09f9ced675f686c15f
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
If unsupported_yuv_input is true, like RK3288, the current logic
will fix the output bus format to MEDIA_BUS_FMT_RGB888_1X24 or
MEDIA_BUS_FMT_RGB101010_1X30, does not changed width the property
hdmi_output_format. This patch fix the issue.
Change-Id: Iddf4182ea8eff066b5f4972c8c3802f7919eb7da
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
cpufreq_interactive_speedchange_task() is running as a separate kernel
thread and is calling __cpufreq_driver_target(), which requires callers
to hold policy->rwsem for writing to prevent racing with other parts of
the kernel trying to adjust the frequency, for example kernel thermal
throttling. Let's change the code to take policy->rwsem and while at it
refactor the code a bit.
This was originally 2 changes reviewed at:
https://chromium-review.googlesource.com/246273https://chromium-review.googlesource.com/256120
Change-Id: Icc2d97c6c1b929acd2ee32e8c81d81fd2af778ab
Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Dmitry Torokhov <dtor@google.com>
Signed-off-by: Liang Chen <cl@rock-chips.com>
RK356X SoCs only support 375KHz for ID mode, otherwise it will be always
failed to set clk if the first attempt to identify cards.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I99ba322b3eeb4c4658869dc88b7a9f303081e12e
The DLL may not be able to lock while the clock rate less than 52mhz.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Ifacc3da516d78f5f242d8b03a60500a7dfe28993
drivers/regulator/xz3216.c: In function 'xz3216_dcdc_set_suspend_mode':
drivers/regulator/xz3216.c:112:3: warning: this statement may fall through [-Wimplicit-fallthrough=]
drivers/regulator/xz3216.c:115:3: warning: this statement may fall through [-Wimplicit-fallthrough=]
drivers/regulator/xz3216.c:165:3: warning: this statement may fall through [-Wimplicit-fallthrough=]
drivers/regulator/xz3216.c:168:3: warning: this statement may fall through [-Wimplicit-fallthrough=]
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I4709021a667a5def61361f27a1675099bcb7b45f
If read the same value three times,
we think this avi patket is correct.
Signed-off-by: Shunqing Chen <csq@rock-chips.com>
Change-Id: I96154c38a79fe142368a2069175fa58fa2d38b0f
The share mem page type should be corresponded with
smccc call.
Change-Id: I2fc97fc6841e2fd6ed7080d6af2fa2929ae355fb
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
