400MHz and 600MHz aren't supported at present.
This had submitted in commit a8c497e79d
("arm64: dts: rockchip: rk3328: Disable 400MHz and 600MHz for dmc")
but was modified in commit 59af91b563
("arm64: dts: rockchip: auto select opp-table by leakage for rk3328")
by mistake.
Change-Id: I864453d16596798e063a2c3569b260fd1a95c209
Signed-off-by: Liang Chen <cl@rock-chips.com>
In the bandwidth tension environment when close win2, vop will access
the freed memory lead to iommu pagefault. so we add this reset to workaround.
Change-Id: I22b0c0f145d042e3aaf98fb45ffff6304c93963c
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Because when enable uboot logo display, vop_crtc_enable() will not be
called when power on, this will lead to some vop initial like
axi channel and some debug irq will not be enabled. so we move some
config to vop_initial() and call from vop_crtc_loader_protect().
Change-Id: I86f02e2e7d12b78cce17e278baaf6dff93137167
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
some version vop unsupport pixel alpha add scale, this case
will lead to display error and post empty.
Change-Id: I32820a14292b46ce61fd30bfccdaa5e4f635de49
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
The most pins of rk3308 are 2bits iomux, but the banks's register
width is 0x8.
Change-Id: I3305810b3f75febd6ec7a933b65e3c9d50f003dd
Signed-off-by: David Wu <david.wu@rock-chips.com>
This adds the necessary data for handling io voltage domains on the rk3308.
As interesting tidbit, the rk3308 contains one iodomain area at grf,
Change-Id: Ife72a284a8926d02ef5df7a422d41924494d0300
Signed-off-by: David Wu <david.wu@rock-chips.com>
Otherwise, clk_gpu won't be disabled actually in the runtime.
Change-Id: I92787a5e23bfb92f5a79efda92c130832751cc3b
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
The commit 9d9491a7da ("mmc: dw_mmc: Fix the DTO timeout calculation")
and commit 4c2357f57d ("mmc: dw_mmc: Fix the CTO timeout calculation")
made changes, which cause multiply overflow for 32-bit systems. The
broken
timeout calculations leads to unexpected ETIMEDOUT errors and causes
stacktrace splat (such as below) during normal data exchange with
SD-card.
| Running : 4M-check-reassembly-tcp-cmykw2-rotatew2.out -v0 -w1
| - Info: Finished target initialization.
| mmcblk0: error -110 transferring data, sector 320544, nr 2048, cmd
| response 0x900, card status 0x0
DIV_ROUND_UP_ULL helps to escape usage of __udivdi3() from libgcc and so
code gets compiled on all 32-bit platforms as opposed to usage of
DIV_ROUND_UP when we may only compile stuff on a very few arches.
Lets cast this multiply to u64 type to prevent the overflow.
Change-Id: I45462bac22f946c5129eab0e0d5b22b3ed7ca19d
Fixes: 9d9491a7da ("mmc: dw_mmc: Fix the DTO timeout calculation")
Fixes: 4c2357f57d ("mmc: dw_mmc: Fix the CTO timeout calculation")
Tested-by: Vineet Gupta <Vineet.Gupta1@synopsys.com>
Reported-by: Vineet Gupta <Vineet.Gupta1@synopsys.com> # ARC STAR
9001306872 HSDK, sdio: board crashes when copying big files
Signed-off-by: Evgeniy Didin <Evgeniy.Didin@synopsys.com>
Cc: <stable@vger.kernel.org> # 4.14
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
(cherry picked from c715160225)
Add the clock tree definition for the new RK3308 SoC.
Change-Id: I1c0794b290207d28102e8d30cca13bbbf54ccfb8
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Add the dt-bindings header for the rk3308, that gets shared between
the clock controller and the clock references in the dts.
Change-Id: I9c6ea1228417f07603d89f810726e9cdffd2a10a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Add devicetree bindings for Rockchip cru which found on
Rockchip SoCs.
Change-Id: Ib28b15d3011704a04294672f82d6a8f855da1536
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
After a cpufreq transition, update the clockevent's frequency
by fetching the new clock rate from the clock framework and
reprogram the next clock event.
The clock supplying the arm-global-timer on the rk3188 is coming
from the the cpu clock itself and thus changes its rate everytime
cpufreq adjusts the cpu frequency.
Found by code review, real impact not known. Assume what actual
HZ value will be different from expected on platforms using
arm-global-timer as clockevent.
The patch is port of commit 4fd7f9b128 ("ARM: 7212/1: smp_twd:
reconfigure clockevents after cpufreq change") and
commit 2b25d9f64b ("ARM: 7535/1: Reprogram smp_twd based on
new common clk framework notifiers").
Change-Id: I82552f621e30254b9c48f22fb3ebd2866d4476c8
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
We found that some Sonix usb cameras(e.g. idVendor=0c45,
idProduct=64ab or idProduct=64ac) can't support auto-suspend
well on rockchip platforms(e.g. rk3399).With auto-suspend,
these usb cameras MJPEG will display abnormally on all usb
controllers(DWC2/DWC3/EHCI). So we need to disable auto-
suspend for these special usb cameras.
Change-Id: I08c87cf5c9fa5ebe076b5dd3e873b74c5ec2cb83
Signed-off-by: William Wu <william.wu@rock-chips.com>
Modify the clock name of EHCI and OHCI controllers, add
property of "status" for OHCI.
Change-Id: I444a906bc26e26989f5f6011de949b816266b9c6
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
for rk322x power down post-PLL must to both set rege0[5]=0 and set
pre pll pre-PLL unlock. So power down pre-PLL before post-PLL power
down
Change-Id: If0eb325b10bb6eb117b0a61d5852e9aae9d92ba6
Signed-off-by: Huicong Xu <xhc@rock-chips.com>
Turn off differential receiver in suspend mode for RK3328 and
PX30 to save power.
The effect of turn off differential receiver on electricity:
USB20_AVDD_1V8: 0.73mA (turn on)
USB20_AVDD_1V8: 0.03mA (tunn off)
Change-Id: I0650d6d4b712a3692eed2564dda36d41b7956bb9
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
we can power off the da_pwrok to reduce power consumption.
Change-Id: Ie08af149e74408e57750a186cf16d5adf4b3cfb7
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
If hdmi is enabled in uboot and pluged out when booting kernel,
the hdmi phy is still enabled. It's better to disable it to
match the real status.
Change-Id: Ia1c5ede6499ee277d08c35a85c50e3257305f90f
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Under following processes, rxsense will be not match the real
signal status.
1. HDMI plug in, irq is triggered.
2. HDMI irq is mute in dw_hdmi_hardirq, bring up dw_hdmi_irq.
3. For HDMI connection is not stable, phy_stat read in
dw_hdmi_irq may be zero, then hdmi->rxsense will be false.
4. Connection fallback to stable, but dw_hdmi_irq had not
unmute the irq, irq is not triggered again, and hdmi->rxsense
keep false.
5. repo_hpd_event inform HDMI is pluggned in, dw_hdmi_bridge_enable
is called to enable HDMI. For rxsense is flase, bridge is not
powered up.
When repo_hpd_event is called, we think HDMI connection is stable,
updating rxsense is reliable.
Change-Id: Ie1f52f65b15e9a603dad9200529202053528a390
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
