from commit: 5b7261b mtd: spinand: winbond: Add support for Winbond W35N01JW SPI NAND flash
Change-Id: Iabca09af99d7b94150c847653faf0275228b7144
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Fixes: 13639746fa ("phy: rockchip: naneng-combphy: Fix swing to 650mv under 100M refclk for rk3562")
Change-Id: If9bf594ec4183d4be62dd1f9edb24ecd30915f78
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Fixes: c3f038c2dc ("PCI: rockchip: dw_ep: Delaying the link training after hot reset")
Change-Id: I9e14995caecce709d93d33b9e2b568a5eae91273
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Assign VOP_ACLK to 750MHZ at rk3588s.dtsi, so reverts this commit 7836b77050.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I1dd48012246eb4d52d748bf489128fcf2885c30f
Assigned RK3588 VOP_ACLK as 750MHZ by default to support 8k output and improve
VOP performance.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ia4c75a9f04c655e4b26867bc87023812cdc7f82f
The I2S-TDM on Rockchip SoCs only support one data lane for tx and one
data lane for rx, but the codec devices may requires a normal tdm work
with more than one data lane.
Enable the TDM_MULTI_LANES to allow driver works under a higher sample
rate and with more data lanes.
More detail, see the driver patch comment.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Idbeeb00d4903e49fb3c0c3dfbb16b55125fe2da7
The former method makes ECC effective value decreased from 4 to 1.
Change-Id: I069e62432bb339356070f5228fc7d65daca7b696
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
The former method makes ECC effective value decreased from 4 to 1.
Change-Id: Ie5f37e291166661def40db015eac63c003719785
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
pinctrl-default/idle/clk must be paired in the same iomux group.
DON'T USE pdm1m0-default with pdm1m1-idle
Ref: commit: 0d9748600792 ("ASoC: rockchip: pdm: Fix clk glitch on runtime PM")
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Iea86fc5a16eaec8b39c31708228732b49ccda5d7
For controller which is managed by PD (power-domain),
when PD off, the controller is reset to the default
status, and the FRAC-DIV is a fixed value(1/20).
Once the mclk is enabled, there are some high freq cycle
leak, to fix this issue, we use the pinctrl-idle to
block these cycles until the config has been come back
to the normal state.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I4e34129277cffa7bc443b6addfb1e26b70bf546e
Define a protocol specification for SPI slave transmission,
with the following main requirements:
1.ctrl packet with 2B cmd, 2B addr(offset in APP_RAM), 4B data
(usually is the following data packet length);
2.data packet with data;
3.support ctrl packet only for configuration;
4.support ctrl packet witch data packet for IO transmission.
5.spidev_rkslv support SPI_OBJ_APP_RAM_SIZE application buffer
Start the test in master device, like following:
echo read 64 1000 > /dev/spidev_rkmst_misc
Show the application buffer in slave device, like following:
echo appmem 0 256 > ./dev/spidev_rkslv_misc
Change-Id: I531e812be56826729345f6718019662fc6f414ae
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
because I2S_SDO2/3 is mux with I2S_SDI3/2.
pinctrl: not freeing pin 58 (gpio1-26) as part of deactivating group i2s0-sdi2
pinctrl: not freeing pin 57 (gpio1-25) as part of deactivating group i2s0-sdi3
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Iba7549712841f21866d4c388a32c5626bfb6af11
pinctrl-default/idle/clk must be paired in the same iomux group.
DON'T USE i2s2m0-default with i2s2m1-idle
Ref: commit: b935bf8cc83f ("ASoC: rockchip: i2s-tdm: Add support for pinctrl idle state")
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I0bf6f1cfb74d7f398050961913439031fa90245f
On the QUIRKS_ALWAYS_ON path, we bring up the clk path on probe
to achieve the clk always on function.
for this situation, the refcount always true, so, we should save
the stream dma state on pause and then do restore on resume.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I8e45b78a475a468880ef2fb0b358dbdd1169ff08
CLK_ALWAYS_ON should be placed after all registers write done,
because this situation will enable XFER bit which will make
some registers(depend on XFER) write failed.
Fixes: 3644caf8de ("ASoC: rockchip: i2s-tdm: Add support for clk always-on")
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Iffcfed18d3805ee575df4e8cf267d4ef6a3fa866
I2S1 has two iomux group, M0 is located in BUS_IOC,
and M1 is located in PMU_IOC. they are controlled by
different IOE bit.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ib6b302e8b03aa7d64bdd11862c413c736eaf4636
register PDM_SYSCONFIG is marked as volatile, and for regcache
sync policy, it will skip the registers which marked as volatile.
so, we should do it after regcache sync.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ic65bc28d14fefc6e6c70e1b2c26468aa0fcd142e
The new hardware design will connect clkreq to the control pin of the
external clock, so the default output should be low level。
Change-Id: I2c99b90b7de359c8f32576d5f6eb7157c7a4a7b5
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This patch enable Schmitt-Trigger for pins I2S-MCLK/BCLK/LRCK for
clk noise reduction on slave mode which clk is provided by external
devices. and this can make controllers work much more robust.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I04237f1b1f56c5abbb4b61f0a2c1af89b1e32bc3
This patch enable Schmitt-Trigger for pins I2S-MCLK/BCLK/LRCK for
clk noise reduction on slave mode which clk is provided by external
devices. and this can make controllers work much more robust.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I619605ee9f71f912e495a2eb991746cdc67d8dd8
This patch enable Schmitt-Trigger for pins I2S-MCLK/BCLK/LRCK for
clk noise reduction on slave mode which clk is provided by external
devices. and this can make controllers work much more robust.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I8734c40041733b51107d0ed9715606111b2b94b9
This patch enable Schmitt-Trigger for pins I2S-MCLK/BCLK/LRCK for
clk noise reduction on slave mode which clk is provided by external
devices. and this can make controllers work much more robust.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Iaac7ecc28e2a686e0c01ff4f3ae082d90fe3474d
This patch enable Schmitt-Trigger for pins I2S-MCLK/BCLK/LRCK for
clk noise reduction on slave mode which clk is provided by external
devices. and this can make controllers work much more robust.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I757328e08969031a638e2f7b7da09bf7473f8a0b
This patch enable Schmitt-Trigger for pins I2S-MCLK/BCLK/LRCK for
clk noise reduction on slave mode which clk is provided by external
devices. and this can make controllers work much more robust.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I08b127b7f75f303c8da45973d068f57b9a6ebc62
This patch enable Schmitt-Trigger for pins I2S-MCLK/BCLK/LRCK for
clk noise reduction on slave mode which clk is provided by external
devices. and this can make controllers work much more robust.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I27ff54d8e17ef9a41cf2db91dbbfb8e81f8227ff
to solve the problem of the camera being unable to restore the default frame rate after adjust it to other frame rates
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: Iedbeca79cb17368922d41a55ef2aafeb58170e1f
