1.ensure hardware is being off status when task done
2.add soft reset process for iep
3.enable hw timeout
4.disable md_pre when md_lambda == 8
Signed-off-by: Chandler Chen <chandler.chen@rock-chips.com>
Change-Id: I700fffddc9a7a2c37b9790d938a243978fa3abdc
"cpu_online_mask" hasn't been cleared yet in CPUHP_AP_ONLINE_DYN stage.
So we use cpumask_any_but instead of cpumask_first.
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: I0a29d18869f50ac584fc545d27045f631045d568
add rkvdec link info for vdpu382 version
Signed-off-by: Chandler Chen <chandler.chen@rock-chips.com>
Change-Id: I7ec36faf021de723257595f0df99cce4722442a0
Try to get the maximum PD revision which Type-C controller can
support from DT, and use this value to init the PD negotiated
revision instead of hard coded values 0x0300 (PD3.0).
This can fix at least the following two Type-C controllers issues:
1. FUSB302 failed to response PD Message "Get Source Cap Ext" if
used the default negotiated revision PD_MAX_REV (PD_REV30)
with MacBook (test on macOS 12.2.1).
2. ET7301B failed to detect the voltage status of the measured
CC pin for vRd-3.0 if used the default negotiated revision
PD_MAX_REV (PD_REV30) with some Type-C DP monitors.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I2c9bcc06ff2b3d678a6eab5013cec7f45cbda3dd
This property is used to tell the maximum USB Power Delivery
revision which Type C controller can support.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ibc0b35096ae270cd6d0e67cbdb2e5b85604f43b3
The Cortex-A76 core supports:
The Armv8.2-A extension.
The RAS extension.
The Load acquire (LDAPR) instructions introduced in the Armv8.3-A extension
The Dot Product support instructions introduced in the Armv8.4-A extension.
The PSTATE Speculative Store Bypass Safe (SSBS) bit and the speculation barriers (CSDB, SSBB,
PSSBB) instructions introduced in the Armv8.5-A extension.
Disable follow ARMv8.3/4/5 features:
-CONFIG_ARM64_PTR_AUTH
-CONFIG_ARM64_AMU_EXTN
-CONFIG_ARM64_TLB_RANGE
-CONFIG_ARM64_BTI
-CONFIG_ARM64_E0PD
-CONFIG_ARCH_RANDOM
-CONFIG_ARM64_MTE
-CONFIG_ARM64_SVE
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I34b8af33b9ed64add2a5e17f6bfa4d3c7601c07f
RK3588 Cortex-A76 version is r4p0.
1188873 Fixed in r3p0.
1165522 Fixed in r3p0.
1286807 Fixed in r3p1.
1463225 Fixed in r4p0.
2054223 Cortex-A710
2067961 Neoverse-N2
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I02b3f71d6b276c6bd1bdce35d8da0838748b954a
The aclk_vio is the vio noc, the HDMI accessed the register
need this clock enabled first. If not, VOP iommu errors will
also occur.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Ib3073b73020e46c7d31b09225dd2bd39a289a4cc
There are one Temperature Sensor on rk3528, channel 0 is for chip.
Signed-off-by: Shaohan Yao <shaohan.yao@rock-chips.com>
Change-Id: Ib5bbb81615fe9fab80f26cdd2098cfb56746ca15
to make sure it take effect in next frame start
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: I4e57ccba704abb9c9a6700f27d5786cb694215dc
When the DMA interrupt masked, the conresbonding DMA interrupt stastus
should be ignored in the interrupt handler.
Change-Id: I76a2b8bef08e024f76792c765150c3e5a0ff804e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Fix performance when BDI's share of ratio is 0.
The issue is similar to commit 74d3694433 ("writeback: Fix
performance regression in wb_over_bg_thresh()").
Balance_dirty_pages and the writeback worker will also disagree on
whether writeback when a BDI uses BDI_CAP_STRICTLIMIT and BDI's share
of the thresh ratio is zero.
For example, A thread on cpu0 writes 32 pages and then
balance_dirty_pages, it will wake up background writeback and pauses
because wb_dirty > wb->wb_thresh = 0 (share of thresh ratio is zero).
A thread may runs on cpu0 again because scheduler prefers pre_cpu.
Then writeback worker may runs on other cpus(1,2..) which causes the
value of wb_stat(wb, WB_RECLAIMABLE) in wb_over_bg_thresh is 0 and does
not writeback and returns.
Thus, balance_dirty_pages keeps looping, sleeping and then waking up the
worker who will do nothing. It remains stuck in this state until the
writeback worker hit the right dirty cpu or the dirty pages expire.
The fix that we should get the wb_stat_sum radically when thresh is low.
Link: https://lkml.kernel.org/r/20210428225046.16301-1-wuchi.zero@gmail.com
Change-Id: I920e60cd938049641eda70885b069e36200fe153
Signed-off-by: Chi Wu <wuchi.zero@gmail.com>
Reviewed-by: Jan Kara <jack@suse.cz>
Cc: Tejun Heo <tj@kernel.org>
Cc: Miklos Szeredi <mszeredi@redhat.com>
Cc: Sedat Dilek <sedat.dilek@gmail.com>
Cc: Jens Axboe <axboe@fb.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from commit ab19939a6a)
This reverts commit 59f45fdccd.
The reason for revert this patch is that mclk_acodec_tx usually keeps
div1 and follows the same value as mclk_i2s0_8ch_tx.
If the DUT is just powered on, the current acodec clk is usually an
uninitialized value (such as 12MHz). At this time, an audio with a
sampling rate of 16kHz needs to be played, and mclk needs 4.096MHz.
The codec set_sysclk() is configured before cpu i2s_sysclk(), set a
div 3 based on target freq 4.096MHz, and then set cpu i2s_sysclk() to
correct the frequency division ratio of parent clock according to
target freq 4.096MHz, and getting the wrong results:
- mclk_i2s0_8ch_tx = 4096000kHz
- mclk_acodec_tx = 1365334kHz
Before:
pll_gpll 1 1 0 1188000000 0 0 50000
gpll 11 11 0 1188000000 0 0 50000
clk_i2s0_8ch_tx_src 1 1 0 594000000 0 0 50000
clk_i2s0_8ch_tx_frac 1 1 0 4096000 0 0 50000
clk_i2s0_8ch_tx 1 1 0 4096000 0 0 50000
mclk_i2s0_8ch_tx 2 2 0 4096000 0 0 50000
mclk_sai 0 0 0 4096000 0 0 50000
mclk_dsm 0 0 0 4096000 0 0 50000
mclk_acodec_tx 1 1 0 1365334 0 0 50000
Fixed:
pll_gpll 1 1 0 1188000000 0 0 50000
gpll 11 11 0 1188000000 0 0 50000
clk_i2s0_8ch_tx_src 1 1 0 594000000 0 0 50000
clk_i2s0_8ch_tx_frac 1 1 0 4096000 0 0 50000
clk_i2s0_8ch_tx 1 1 0 4096000 0 0 50000
mclk_i2s0_8ch_tx 2 2 0 4096000 0 0 50000
mclk_sai 0 0 0 4096000 0 0 50000
mclk_dsm 0 0 0 4096000 0 0 50000
mclk_acodec_tx 1 1 0 4096000 0 0 50000
Therefore, we only need to set_sysclk() once on the rockchip i2s driver.
Change-Id: I8e3d32ec1061166faa8188e6288934867880ab48
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
According to upstream commit e9b6044dce ("arm64: dts: remove g-use-dma
from rockchip usb nodes").
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Iffe9e52c68507b7bea2ab86306519910a2db9d16
RK3528 can only support up to 8 MSI vectors, add a limitation
for that.
Change-Id: I62297711053253b8548cf61d69fbd9bcf690114d
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ic7bc74c1a05b06c45f83bdb7056a8c4b206dd4dd
[Shawn: squash commit fa7b48efe743 ("PCIe: dw: rockchip: Do not free msi in PM ops")]
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
ss_n be high for half or one sclk_out cycle after every frame data
is transferred
Change-Id: I08aa4e0b76dd2bf5695608740b0cb0989f75eaed
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
-# CONFIG_AUDITSYSCALL is not set
-# CONFIG_ROCKCHIP_ONE_INITRD is not set
-CONFIG_RTL8723CS=m
-CONFIG_RTL8821CS=m
-CONFIG_RTL8822BS=m
-CONFIG_LTE=y
-CONFIG_LTE_RM310=y
-CONFIG_RK3368_THERMAL=y
-CONFIG_REGULATOR_DIO5632=y
-CONFIG_VIDEO_GC0312=y
-CONFIG_VIDEO_OV5648=y
-CONFIG_VIDEO_VM149C=y
-CONFIG_SND_SOC_ROCKCHIP_RT5651=y
-CONFIG_SDIO_KEEPALIVE=y
-CONFIG_POWERVR_ROGUE_N=y
-CONFIG_RK3368_MBOX=y
-CONFIG_RK3368_SCPI_PROTOCOL=y
-CONFIG_SDCARD_FS=y
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I9ad2e626d1d7125830fca09791158ad6cd8910fc
