Original vop show required 64 pixel aligned for width,
but now all resolution are scale to 1920x1080 or
1088x1920 for 90/270 degree rotation is 64 aligned;
so rga blit is no needed to do 64 aligned limit, fix it.
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: I42433009182d1f29372a0ebe4f7482f9b82a64f6
if too many mipi err print in irq, it cause system stuck,
so use workqueue to print mipi err to fix it.
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: I8bf29f3dc17c1e1b722fad6b2b3841db71e17dca
The rtc alarm status must be cleared after alarm 1s or after the alarm
is disabled.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I0874a24d1a3c0e7fd5e8462871d508392f7853cc
When UVC gadget as bulk mode connect to Linux (tested on Ubuntu 18.04),
it may occur twice set_alt for streaming interface, and the UVC state
is moved to "UVC_STATE_STREAMING" before process stream on event, so
amend to check the uvc state value to fix stream on error return.
Fixes: d471d7168a ("usb: gadget: uvc: fix NULL pointer dereference when usb hotplug")
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: Ib0d65c161d8680186ae26b2c8a0f6116b599c158
According to the SI report, set default drive strength
as below:
clk level_4
den level_3
hsync level_3
data0-23 level_3
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Ie14bb84e485c87a6f153bf0b23e13adeb21dadca
At interlace mode, the adjusted_mode->crtc_vdisplay will be div2 from vdisplay,
but the userspace is still set as adjusted_mode->vdisplay.
Fixes: bfc49df515 ("drm/rockchip: vop3: plane display size check use crtc_* parameter is more correct")
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I6765e5486dc4d15b0b34b75370280d48500ef4da
1.Double OIP=0 after page 13H
2.The nand flash does not support 84H and 34H command
Change-Id: Ie805f42a36e1a864115988087bdc43592cc94ded
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Fix 2 issue:
1.The array_index_nospec will clamp the index within the range of
[0, size).If no core is idle, it still return core_id = 0 that will
cause core 0 dispatch to work.
2.Disable a core dose not take effect.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I939b0eee16fcec495b8cfe87aff3cb3e59044e5e
The FBS feature may not be re-enabled if an error occurred
during soft reset. If the host supports FBS, this patch will
re-enable FBS at the end of soft reset.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I821bf5362c6be8ddf142823ad6b6268c797bcded
1/ disable CONFIG_DM_VERITY
On Linux OS, it is not necessary to enable CONFIG_DM_VERITY by default,
only required if secureboot or security related functions are enabled.
2/ adjusting the config order
make ARCH=arm menuconfig, then make ARCH=arm savedefconfig
to check.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: If0c11c32bf3ea42a36fa7fa12fbd9cc4a464e200
from commit: 5b7261b mtd: spinand: winbond: Add support for Winbond W35N01JW SPI NAND flash
Change-Id: Iabca09af99d7b94150c847653faf0275228b7144
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Fixes: 13639746fa ("phy: rockchip: naneng-combphy: Fix swing to 650mv under 100M refclk for rk3562")
Change-Id: If9bf594ec4183d4be62dd1f9edb24ecd30915f78
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Fixes: c3f038c2dc ("PCI: rockchip: dw_ep: Delaying the link training after hot reset")
Change-Id: I9e14995caecce709d93d33b9e2b568a5eae91273
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Assign VOP_ACLK to 750MHZ at rk3588s.dtsi, so reverts this commit 7836b77050.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I1dd48012246eb4d52d748bf489128fcf2885c30f
Assigned RK3588 VOP_ACLK as 750MHZ by default to support 8k output and improve
VOP performance.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ia4c75a9f04c655e4b26867bc87023812cdc7f82f
The I2S-TDM on Rockchip SoCs only support one data lane for tx and one
data lane for rx, but the codec devices may requires a normal tdm work
with more than one data lane.
Enable the TDM_MULTI_LANES to allow driver works under a higher sample
rate and with more data lanes.
More detail, see the driver patch comment.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Idbeeb00d4903e49fb3c0c3dfbb16b55125fe2da7
The former method makes ECC effective value decreased from 4 to 1.
Change-Id: I069e62432bb339356070f5228fc7d65daca7b696
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
