PPLL 100M use refdiv =1 fbdiv = 150, postdiv1= 6,
postdiv2=6, vco= 3.6G, is best for pcie.
Change-Id: I40eb1a71c5025a68cab65ec56d2c2a7725d30c63
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This patch fixes the following warning:
drivers/i2c/busses/i2c-rk3x.c:1136 rk3x_i2c_xfer() error: uninitialized symbol 'timeout'.
Fixes: d5635ca05b ("i2c: rk3x: Disable irq after i2c transfer finished")
Change-Id: I7618ae660a62e8e3fc5b7b5d00cff1264bd18663
Signed-off-by: David Wu <david.wu@rock-chips.com>
The system tick may be modified by NTP when we connect
with network, then jiffies have an offset compared to
the local clock, it will cause the irq_pos / delta_play /
delta_capt also be inaccurate.
Therefore, we need a way to get raw jiffies which follows
local raw clocks.
Change-Id: I9be1790dfd98e430982dad6f03b04532889279a6
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
It's found a new r8169 ethernet card with a device ID of
0x0000 read from its config header which wasn't in the
ID tables of r8169. Add it in order to probe this card.
Change-Id: I27c542a10cc571a6e1a4e7a8af62ce560b8b1fc4
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
The DWC3 with Innosilicon USB 3.0 PHY on Rockchip platforms
(e.g. rk3328, rk1808) has problem to exit to U0 state from
U1 or U2 state when DWC3 work as peripheral mode. This patch
adds a quirk to reject transition to U1 and U2 state to
workaround this issue.
Change-Id: Ib5a7a603193df23e4d274681bad155d005238349
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch adds a quirk for some special platforms (e.g.
rk1808 platform) which has problem to exit to U0 state
from U1 or U2 state when dwc3 work as peripheral mode.
To workaround this issue, we can add this quirk to reject
transition to U1 and U2 state.
Change-Id: I611b3562800e77079193cd5e96f6fe30bb3ca88a
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch fix the aloop card index to 7, and leave the card 0
place for default hw snd card.
Change-Id: I767d3d61b1ecb09b813d7bf81b99298cd30a3969
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This patch make the waterlevel more reasonable, because the pdm
controller share the single FIFO(128 entries) with each channel.
adjust waterlevel in frame to meet the vad or dma frames request.
Change-Id: I9b5808e55025347d435f47889f39ba34ac07ea1c
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
fix the vts error like this:
Failed to parse! Parsing error at token LexToken(COMMA,',',1,48) in line 1;
explain:
the vts will parsing the codec'name after android P, the comma is not allow
in the codec'name
Change-Id: I6cb011331368d64417bd9955ba5d3deb84d49b8d
Signed-off-by: Xinhuang Li <buluess.li@rock-chips.com>
On rk3399 platforms, Type-c1 can be simplified to Type-A
port and support USB 3.0 Host only mode. It has a problem
that the dwc3_rockchip_resume() will reset the controller
upon pm resume, and this may cause usb device(e.g. usb 4G
modem) to be reenumerated. This patch sets the flag of
connected to true and avoid to do the reset operation upon
pm resume.
Change-Id: I57f92d0277a19ce1c7b881fe2da6470fd3a70b73
Signed-off-by: William Wu <william.wu@rock-chips.com>
According to the PHY datasheet of rtl8211f, if the reset time
of the PHY is not enough, it will cause the PHY instability,
which has been encountered by other customers, need to take
longer than rtl8211e.
Change-Id: I2786c8b9005a3437d39d6b580d01f03c590848d6
Signed-off-by: David Wu <david.wu@rock-chips.com>
Make of_devfreq_cooling_register_power() as static inline.
This fixes the building error when CONFIG_THERMAL is disabled.
Change-Id: I3d88a3679de279a7ee7eadae7243b9661fdddf75
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
In some case，log like this:
[ 12.393926] rk3x-i2c ff150000.i2c: irq in STATE_IDLE, ipd = 0x51
[ 12.416592] rk3x-i2c ff150000.i2c: irq in STATE_IDLE, ipd = 0x51
The i2c clock is disabled, so the pending irq clean is not
worked. Disable the interrupt after the i2c jobs were done,
the error log would not happen.
Change-Id: If04a2e2214d675410c67db0f131ee7ef635ddcb4
Signed-off-by: David Wu <david.wu@rock-chips.com>
If the slave hold the scl low for a long time, we will send
the stop because the i2c transfer is timeout. Then reset the
slave, the scl will be released to high by slave, the data
hold low, but the controller's state is messy now, need to
diable i2c controller, it is better to reset i2c controller,
it will go back to normal state.
The log like this:
[ 117.444700] rk3x-i2c ff3d0000.i2c: timeout, ipd: 0x93, state: 2
[ 118.466410] rk3x-i2c ff3d0000.i2c: timeout, ipd: 0x00, state: 1
[ 119.486217] rk3x-i2c ff3d0000.i2c: timeout, ipd: 0x00, state: 1
or
[ 91.733176] rk3x-i2c ff3d0000.i2c: timeout, ipd: 0x80, state: 1
[ 103.406776] rk3x-i2c ff3d0000.i2c: timeout, ipd: 0x00, state: 2
[ 104.426636] rk3x-i2c ff3d0000.i2c: timeout, ipd: 0x00, state: 2
Change-Id: I53e6e383c849cea22d870f9488c23720e74115df
Signed-off-by: David Wu <david.wu@rock-chips.com>
Add a quirk to avoid USB 3.0 PHY enter suspend mode when
the dwc3 controller suspend conditions are valid, it can
help to fix the dwc3 initialization error issue with the
following log:
dwc3 fd000000.dwc3: failed to enable ep0out
Change-Id: Iedcb9fa6c2c7fe923839362e35267fedb55889a7
Signed-off-by: William Wu <william.wu@rock-chips.com>
