Make it possible to use the bulk API with optional supplies, by allowing
the consumer to marking supplies as optional in the regulator_bulk_data.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 3ff3f518a1)
Change-Id: I1bf21d36ca181932bf7c626d45fef49b50931ac9
Signed-off-by: David Wu <david.wu@rock-chips.com>
According to the dw-hdmi spec, colorspace in bits 0,1,7,
scan_mode in bits 4,5.
Change-Id: I45233316ea7d5ce75d3844c183654f161cbf505e
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
The "clock-freq-min-max" property was deprecated.
There is "max-frequency" property in drivers/mmc/core/host.c
"max-frequency" can be replaced with "clock-freq-min-max".
Minimum clock value might be set to 100K by default.
Then MMC core should try to find the correct value from 400K to 100K.
So it just needs to set Maximum clock value.
Change-Id: I1c72a891c8afd221b0c395c32c7adf8696cc46f1
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit b023030f10)
If there is no property "clock-freq-min-max", mmc->f_min should be set
to 400K by default. But Some SoC can be used 100K.
When 100K is used, MMC core will try to check from 400K to 100K.
Change-Id: I059c994f1654c212bcff9b85dbffd9697d800eaf
Reported-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 72e83577bc)
HDMI 2.0 introduces a new sampling mode called YCbCr 4:2:0.
According to the spec the EDID may contain two blocks that
signal this sampling mode:
- YCbCr 4:2:0 Video Data Block
- YCbCr 4:2:0 Video Capability Map Data Block
The video data block contains the list of vic's were
only YCbCr 4:2:0 sampling mode shall be used while the
video capability map data block contains a mask were
YCbCr 4:2:0 sampling mode may be used.
This RFC patch adds support for parsing these two new blocks
and introduces new flags to signal the drivers if the
mode is 4:2:0'only or 4:2:0'able.
The reason this is still a RFC is because there is no
reference in kernel for this new sampling mode (specially in
AVI infoframe part), so, I was hoping to hear some feedback
first.
Tested in a HDMI 2.0 compliance scenario.
Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Cc: Carlos Palminha <palminha@synopsys.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: David Airlie <airlied@linux.ie>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-kernel@vger.kernel.org
(am from https://patchwork.kernel.org/patch/9495175)
Change-Id: I7c9e331b5bf5f1fbcefd4368bc4b82ff180eb91e
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
CEA-861-F specs defines new 4k video modes to be used with
HDMI 2.0 EDIDs. These modes start at VIC=93 and go all the
way till VIC=107.
Our existing CEA modedb contains only 64 modes (VIC=1 to VIC=64). Now
to be able to parse 4k modes using the existing techniques, we have
to complete the modedb (VIC=65 onwards).
This patch adds:
- Timings for existing CEA video modes (from VIC=65 till VIC=92)
- Newly added 4k modes (from VIC=93 to VIC=107).
Cc: Jose Abreu <Jose.Abreu@synopsys.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Andrzej Hajda <a.hajda@samsung.com>
V2: Addressed review comments from Jose:
- fix the timings for VIC 83, 90 and 91
- fix formatting for VIC 93-107
V3: Rebase on drm-tip
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Jose Abreu <Jose.Abreu@synopsys.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
(am from https://patchwork.kernel.org/patch/9543865/)
Change-Id: I3708db9a06a1d57c4714aed67fb7ef3711ea0d1e
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Add a dummy entry to CEA/HDMI mode tables so they can be indexed
directly using the VIC, avoiding a +1/-1 dance here and there. This adds
clarity to the error checking for various functions that return the VIC
on success and zero on failure; we can now explicitly check for 0
instead of just subtracting one from an unsigned type.
Also add drm_valid_cea_vic() and drm_valid_hdmi_vic() helpers for
checking valid VICs.
v2: add drm_valid_cea_vic and drm_valid_hdmi_vic helpers (Ville)
use { } instead of { 0 } for initializing the dummy modes
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1452252111-6439-1-git-send-email-jani.nikula@intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Change-Id: Id47deb7a806b896c047317ca8924ef73abb01095
(cherry picked from commit d9278b4c2c)
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Rather than using drm_match_cea_mode() to see if the EDID detailed
timings are supposed to represent one of the CEA/HDMI modes, add a
special version of that function that takes in an explicit clock
tolerance value (in kHz). When looking at the detailed timings specify
the tolerance as 5kHz due to the 10kHz clock resolution limit inherent
in detailed timings.
drm_match_cea_mode() uses the normal KHZ2PICOS() matching of clocks,
which only allows smaller errors for lower clocks (eg. for 25200 it
won't allow any error) and a bigger error for higher clocks (eg. for
297000 it actually matches 296913-297000). So it doesn't really match
what we want for the fixup. Using the explicit +-5kHz is much better
for this use case.
Not sure if we should change the normal mode matching to also use
something else besides KHZ2PICOS() since it allows a different
proportion of error depending on the clock. I believe VESA CVT
allows a maximum deviation of .5%, so using that for normal mode
matching might be a good idea?
Change-Id: I824ec50368ddf152c9daa747ba92aaba1ef50f4b
Cc: Adam Jackson <ajax@redhat.com>
Tested-by: nathan.d.ciobanu@linux.intel.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92217
Fixes: fa3a7340ea ("drm/edid: Fix up clock for CEA/HDMI modes specified via detailed timings")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit 4c6bcf4454)
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Also fix io_domains and pmu_io_domains on rk3368-tb.dtsi
Change-Id: I90867a839079f67c68b8588304e06f7566749a3d
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
Using the builtin I2C controller in dw_hdmi is better than using the
normal RK3288 I2C controller(I2C5).
TEST: work normally when switch mode between 4K@60hz|4K@30hz|1080P..
Change-Id: Ic7287f9a87f0d701a10cbb94f6ae9f11f981739c
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
This patch do the following operation with scdc:
1、TMDS Configuration
set TMDS_Bit_Clock_Ratio bit when supports TMDS Bit Rates
above 3.4 Gbps
(details see HDMI2.0 Specification Section 6.1.3.2)
2、Scrambling Control
set Scrambling_Enable bit when it needs.
(details see HDMI2.0 Specification Section 6.1.3.1)
Change-Id: Ibd4428bdf752d767caf9dd4e03f3c8d240f18f6b
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
HS400-ES devices fail to initialize with the following error messages.
mmc1: power class selection to bus width 8 ddr 0 failed
mmc1: error -110 whilst initialising MMC card
This was seen on Samsung Chromebook Plus. Code analysis points to
commit 3d4ef32975 ("mmc: core: fix multi-bit bus width without
high-speed mode"), which attempts to set the bus width for all but
HS200 devices unconditionally. However, for HS400-ES, the bus width
is already selected.
Change-Id: I877b225a2ab9da623061288b2f908e956754107a
Cc: Anssi Hannula <anssi.hannula@bitwise.fi>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Brian Norris <briannorris@chromium.org>
Fixes: 3d4ef32975 ("mmc: core: fix multi-bit bus width ...")
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Shawn Lin <shawn.lin@rock-chip.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
The TRM says the vendor ID in the RC's configure space can be rewritten
and the value must be the same as the value read from the local core
configure space. But we misread that and didn't notice it before. Actually
we should only able to rewrite it from the local core configure space.
Fix that issue to make lspci show the correct IP vendor infomation.
Change-Id: Ia33bc0c10970649cc86bd02136f0ee997f18246d
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
(cherry picked from 5800790a92)
We enable it by default as we could see the usage of PCB layout
will not stuff this registor. For currently boards which soldered
it already, there should be no harmful.
Change-Id: I913d6412d9e4589ded5ca012e46fe3e93075cc0d
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>
Move some Android only nodes to rk3368-android.dtsi
Change-Id: I6fe283d4c247479945fbc3396cc65392268a2731
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
Add the supply-links according to the R88 schematics.
Change-Id: Ia5119019d9d8b3d2d1990119f0947eaa0b901586
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 39e5f7bb98)
Add the core io-domain nodes to grf and pmugrf which individual
boards than just have to enable and add the necessary supplies to.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit d1ab05aba9)
Change-Id: Ib70f0195544466b089866ac31eb9ea6fe73c5d59
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
The general register files do contain a lot of separate functions and
while some really are only registers with a lot of different 1-bit
settings, there are also a lot of them containing some bigger function
blocks. To be able to define these as sub-devices, make them simple-mfds.
Change-Id: I666e4fe9e6239a91ccaa70154883128be34f17c6
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 4cca3d9448)
In order to be standard to manage for rockchip SoCs, move the thermal
data into rk3368 dtsi, we needn't to add a new file for thermal.
Change-Id: I4cadb8742fb103f5642a8d122ebb5970eb140d30
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: Eduardo Valentin <edubezval@gmail.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 6ddf93e05e)
The GeekBox contains an MXM3 module with a Rockchip RK3368 SoC.
Some connectors are available directly on the module.
This adds initial support, namely serial, USB, GMAC, eMMC, IR and TSADC.
Change-Id: Ic9956b3b935467e3492bdab274579d4cd038d4e6
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit fd7b980c9e)
This adds mailbox device nodes in dts.
Mailbox is used by the Rockchip CPU cores to communicate
requests to MCU processor.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 6e7f9f5ad5)
Change-Id: I9b93b2b3c28ca686c297d839077df5d725436f2f
This patch fixes the incorrect Over-temperature protection pin.
since the rk3368 io list said the otp pin is gpio0a3.
Anyway, that should be fixed in here.
Change-Id: I0b868b6a2e1aac3eea21d6de4787b169a53ade5e
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 04317584ff)
Add tuning clk for emmc and sdmmc, otherwise I get
the following failure while enabling mmc-hs200-1_8v.
dwmmc_rockchip ff0f0000.dwmmc: Tuning clock (sample_clk) not defined.
mmc0: tuning execution failed
mmc0: error -5 whilst initialising MMC card
With it
dwmmc_rockchip ff0f0000.dwmmc: Successfully tuned phase to 170
mmc0: new HS200 MMC card at address 0001
mmcblk0: mmc0:0001 M8G1GC 7.28 GiB
Change-Id: I14534f43249edecbb8239f4a86c808ebb7f0a959
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 90191625ec)
There is a need of a broadcast timer in this case to ensure proper
wakeup when the cpus are in sleep mode and a timer expires.
Change-Id: I8ab0e5506420e2650acc1dac4d5667f40c0d3b4f
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit b8084e5b34)
The card detect pin is currently called sdmcc-cd.
This patch fixes the typo and renames the pin to sdmmc-cd.
Change-Id: I47ac2767ea442764bf71411ebd66de56e9c1e934
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 8fc5abd40e)
In general, the logic voltage is affected by ddr frequency factors.
We should fix the correct voltage range since assuemd that we have the
ddr frequency driver in mainline.
AFAIK, the 1.8v voltage is used by the SD3.0 card.
Change-Id: Id0ae87c7ec6d3d757fdde0b85caf1f535d200222
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 87ac9de3b4)
This board is similar with the rk3288 evb board but the rk3368 top
board. There exist the act8846 as the pmic.
Moment, add the balight/thermal/emmc/usb.. stuff,
Let the board can happy work.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 5378e28c97)
Change-Id: I78f39fa080d221e06849285b6a0c52bc04d5d1a9
This patch add the thermal needed info on RK3368.
Meanwhile, support the trips to throttle for thermal.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit f990238f85)
Change-Id: I76ba5230b1a334562ce7607aa02fec445612070c
Add an ethernet0 alias for the RK3368 mac interface so
that u-boot can find the device-node and fill in the mac address on
boards that support a wired network interface.
Change-Id: I2f82939290a0807ed84a3e93f6b0eef879cce076
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit ff08868ef0)
RK808_ID_DCDC1 is 0, no need to do subtract RK808_ID_DCDC1.
Change-Id: I395c30866aeb5c4c285dd083109a70bfef24bfca
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit bf8e27621e)
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add support for the rk818 regulator. The regulator module consists
of 4 DCDCs, 9 LDOs, 1 switch and 1 BOOST converter which is used to
power OTG and HDMI5V.
The output voltages are configurable and are meant to supply power
to the main processor and other components.
Change-Id: I129a1f22c65684615e9ae792efaa880555f0235e
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
(cherry picked from commit 1137529353)
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The field "owner" is set by core. Thus delete an extra initialisation.
Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
Change-Id: I7a2e347e07943c7eb5b2c9cae4eae2358a613e0e
(cherry picked from commit 556ae220ac)
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
A common simplified DT parsing code for regulators was introduced in
commit a0c7b164ad ("regulator: of: Provide simplified DT parsing
method")
While at it also added RK8XX_DESC and RK8XX_DESC_SWITCH macros for the
regulator_desc struct initialization. This just makes the driver more compact.
Change-Id: I5c1211decf37d27a68167be9b6354834532cc87b
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 9e9daa0a67)
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
LDO_REG3 descriptor is using linear_ranges.
Add and use proper ops for LDO_REG3.
Change-Id: Iad515fd23e7b3bca6248739a54335a71eed01238
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 129d7cf98f)
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
After removing all uses of the range operations in a recent patch,
we get a warning about the symbol not being referenced anywhere:
drivers/regulator/rk808-regulator.c:306:29: 'rk808_reg_ops_ranges' defined but not used
This removes the now-unused structure along with the
rk808_set_suspend_voltage_range function that is only referenced from
rk808_reg_ops_ranges.
Fixes: afcd666d9d ("regulator: rk808: remove linear range definitions with a single range")
Change-Id: I565c91186ab5d7457a62b3bc4b4896a08f39dd2e
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 4a5ed8c1ad)
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The driver was using only linear ranges. Now we remove linear range
definitions with a single range. So we have to add an ops struct for
ranges and adjust all other ops functions accordingly.
Change-Id: I6b2dd5e035832f9460ec8a24b5214204f7a930b7
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit afcd666d9d)
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
default enable rkvdec and vpu.
rga is default on, remove duplicate configuration.
Change-Id: I8375b2202a81977238e8120e1c2d60f2130844b5
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
