Parse boot mode on system bootup, and export it to
userspace by sysfs: sys/kernel/boot_mode
Change-Id: I0158fc28f4dae51c798806006e49cead4ce2e923
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
The power_allocator thermal governor should get utilization of cooling
device to calculate dynamic power, but the powersave, userspace and performance
devfreq governor don't updade stats, so the utilization is inaccurate.
This patch adds support to update status when get requested power, so that
power_allocator can also work properly when use powersave, userspace and
performance devfreq governor.
Change-Id: Ic98fabf46f693a60b0f07094c59e75e4d141e42c
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
As policy->cur may be changed by thermal and cpufreq_suspend, the setspeed
may be changed after resume.
Change-Id: I6d4e0672ff39127c522f305719afd52806c31f48
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
vop iommu handled by vop driver, so ignore the iommu operation when vop
call pm_runtime_get_sync/pm_runtime_put_sync
Change-Id: I126661e56f16b1740793dcc49340518094eee514
Signed-off-by: Simon Xue <xxm@rock-chips.com>
iommu may enabled by pm_runtime_get_sync from vop, this
path is not accept by vop, so ignore device_link for vop
Change-Id: I532a2a964b423e78fadec02c3b4c2952301ebf4b
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Add mailbox and scpi protocol function support for rk3368 SoC.
Change-Id: I201c916865eb2729ed135c3f5a77a9dd97007952
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
In .remove progress, EP and RC driver may access EP via PCIe, don't
do really hardware access, just ignore.
Change-Id: Ide5831c2cdcabea6c289b1eb96d6f80294f94ac8
Signed-off-by: Simon Xue <xxm@rock-chips.com>
After a cpufreq transition, update the clockevent's frequency
by fetching the new clock rate from the clock framework and
reprogram the next clock event.
The clock supplying the arm-global-timer on the rk3188 is coming
from the the cpu clock itself and thus changes its rate everytime
cpufreq adjusts the cpu frequency.
Found by code review, real impact not known. Assume what actual
HZ value will be different from expected on platforms using
arm-global-timer as clockevent.
The patch is port of commit 4fd7f9b128 ("ARM: 7212/1: smp_twd:
reconfigure clockevents after cpufreq change") and
commit 2b25d9f64b ("ARM: 7535/1: Reprogram smp_twd based on
new common clk framework notifiers").
Change-Id: I82552f621e30254b9c48f22fb3ebd2866d4476c8
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
strlcpy(clkin_name, __clk_get_name(clk), sizeof(clkin_name));
the clkin_name will wrong when clk is clk_i2s0_8ch_tx_out
Change-Id: If5603b5c31d4705289d075b2b375a35f3d4e4178
Signed-off-by: Yu YongZhen <yuyz@rock-chips.com>
The "host1" port (AKA the dwc2 port that isn't the OTG port) on rk3288
has a hardware errata that causes everything to get confused when we get
a remote wakeup. We'll use the reset that's in the CRU to reset the
port when it's in a bad state.
Note that we add the reset to both dwc2 controllers even though only one
has the errata in case we find some other use for this reset that's
unrelated to the current hardware errata. Only the host port gets the
quirk property, though.
Change-Id: I472d33fb1db8b1a6b0c4fcea9ab31fd85b61af40
Signed-off-by: Randy Li <ayaka@soulik.info>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9324169/)
Make of_devfreq_cooling_register_power() as static inline.
This fixes the building error when CONFIG_THERMAL is disabled.
Change-Id: I3d88a3679de279a7ee7eadae7243b9661fdddf75
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
This patch adds NoC (Network on Chip) Probe driver which provides
the primitive values to get the performance data. For example, RK3399
has multiple NoC probes to monitor traffic statistics for analyzing
the transaction flow.
Change-Id: I66f6708f0d244488ca08f0f1f1cb36b19c7a2d0a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Calculate current load with busytime / totaltime from status,
also show the current frequency.
Change-Id: Ic310035db9c5478aa3d0b1e526b47c451fe09d23
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
In order to fix deadlock between dmcfreq and vop on/off,
When change vop status and ddr frequency at the same time,
the following deadlock will happen:
vop no/off dmcfreq
vop_crtc_disable update_devfreq
->mutex_lock(&vop->vop_lock); ->mutex_lock(&pd->pmu->mutex);
->pm_runtime_put(vop->dev); ->mutex_lock(&vop->vop_lock);
->mutex_lock(&pd->pmu->mutex); ...
Change-Id: I56a4ee944200826d2a09e3ae8d2f4837f6f769d6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
The usb phys need to be controlled dynamically on some Rockchip SoCs.
So set the new HCD flag which prevents USB core from trying to manage
our phys.
Change-Id: I2d1197f42fe49bc4e454954481f344256fddb557
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Power down feature of DWC2 module integrated in Rockchip SoCs doesn't work
properly or needs some additional handling in PHY or SoC glue layer, so
disable it for now. Without disabling power down, DWC2 sporadically cannot
detect USB disconnect.
Change-Id: Ic46fdb7a000b9029727a6a46e4ca5399b98285e8
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
The dwc2 programming guide section 3.5 'Halting a Channel'
says that the application can disable any channel by
programming the HCCHARn register with the HCCHARn.ChDis
and HCCHARn.ChEna bits set to 1'b1. This enables the
dwc_otg host to flush the posted requests (if any) and
generates a Channel Halted interrupt.
But it also requires that channel disable must not be
programmed for non-split periodic channels. At the end
of the next uframe/frame (in the worst case), the core
generates a channel halted and disables the channel
automatically.
If we disable non-spilt periodic channels to halt the
channels, it will easily to cause data transfer fail.
A typical case is take photo with usb camera or close
usb camera, Specifically, the observed order is:
1. uvc driver calls usb_kill_urb
2. usb_kill_urb calls urb_dequeue to cancel urb
3. urb_dequeue call dwc_otg_hc_halt to disable
non-spilt periodic channels
4. usb core doesn't halt the non-spilt periodic
channels immediately, and the application
reallocates the channels for other transactions
without waiting for the HCINTn.ChHltd interrupt.
5. uvc driver calls usb_set_interface to start
control transfer, and gets a channel which used
for non-spilt periodic transfer before. The core
generates a channel halted and disables the channel
automatically. This cause control transfer fail.
Change-Id: I95424a99b77b552396a9fb95a5058258270ed4c2
Signed-off-by: William Wu <william.wu@rock-chips.com>
The commit e6f2f6d63e ("usb: dwc2: power on/off phy for
otg mode") aimed to control phy power for otg mode, but
it also introduced a new problem, so we fix it.
This patch keep phy power on for otg if current mode is
host during dwc2 probe, otherwise the enumeration will
fail with the following error log:
Cannot enable. Maybe the USB cable is bad?
Cannot enable. Maybe the USB cable is bad?
attempt power cycle
Cannot enable. Maybe the USB cable is bad?
Cannot enable. Maybe the USB cable is bad?
unable to enumerate USB device
Fixes: e6f2f6d63e ("usb: dwc2: power on/off phy for otg mode")
Change-Id: I17a4cab6f0337fdc0923989aea8613bfbe1a9e9b
Signed-off-by: Feng Mingli <fml@rock-chips.com>
The frame_overrun flag is used to indicates
SOF number (current_frame) overrun in DSTS
and the target_frame over DSTS_SOFFN_LIMIT.
Clear the frame_overrun flag only if target_frame
below DSTS_SOFFN_LIMIT and current_frame less
than target_frame.
Change-Id: I91cf9001324a9bbbcc4bc28b335695d607fb69d4
Signed-off-by: William Wu <william.wu@rock-chips.com>
Adds pm_runtime support for dwc2, so that power domain is
enabled only when there is a transaction going on to help
save power.
Change-Id: I318552774d20eeaed521ff179f99b2551ee24183
Signed-off-by: William Wu <william.wu@rock-chips.com>
When a usb device disconnects in a certain way, dwc2_queue_transaction
still gets called after dwc2_hcd_cleanup_channels.
dwc2_hcd_cleanup_channels does "channel->qh = NULL;" but
dwc2_queue_transaction still wants to dereference qh.
This adds a check for a null qh.
(am from https://patchwork.kernel.org/patch/7245251/)
Change-Id: Ia9c7f5febe0bb6f0123cfc85c90beb9fc1d80bdd
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
The operation mode of controller will change to peripheral when
resume if PD is power off during suspend, current code disconnect
hcd and set lx state to L3 in this case to make sure the controller
will be reinit in device mode, but that's not enough, the op_state
is still host which is change when init or ID change interrupt
occur. If the ID change happened after suspend the driver would
miss the interrupt, so when the application call the pullup function
to stop gadget and start again to change to another function, the
disconnect gadget operation can't be done and the gadget restart
directly. This will result in NULL point when gadget work. This
patch set op_state to OTG_STATE_B_PERIPHERAL when resume in this
case.
Change-Id: Ifbafb7fae43d634cfa879c9a066d1e114db4196e
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
The controller will reset and run into error state if turn
off power when suspend in host mode. This patch stop hcd to
make the controller into L3 state to make sure that the
controller and driver state will reset when resume.
Change-Id: If66bc1a249e919f440ecde0c66f18dabde0b2e62
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
The commit dc71e51944 ("usb: dwc2: make otg manage lowlevel
hw on its own") aimed to control the clk and phy power for
otg mode, but it also introduced lost of new problems, so we
revert it.
This patch only controls phy power for otg mode, it can fix
the dwc2 udc start fail issue with the following error log:
dwc2_hsotg_init_fifo: timeout flushing fifos (GRSTCTL=80000430)
dwc2_core_reset() HANG! Soft Reset GRSTCTL=80000001
bound driver configfs-gadget
dwc2_core_reset() HANG! Soft Reset GRSTCTL=80000001
Change-Id: Id6996aecab7f0aaaf12530b7a377144e23ef1667
Signed-off-by: William Wu <william.wu@rock-chips.com>
When handle disconnect of the hcd during bus_suspend, hcd
needs to resume its root hub, otherwise the root hub will
not disconnect the existing devices under its port.
This issue always happens when connecting with usb devices
which support auto-suspend function (e.g. usb hub).
(am from https://patchwork.kernel.org/patch/9751469/)
Change-Id: I663fdea73f36e89130d9a250612363968cbff941
Signed-off-by: William Wu <william.wu@rock-chips.com>
Originally, dwc2 just handle one clock named otg, however, it may have
two or more clock need to manage for some new SoCs, so this adds
change clk to clk's array of dwc2_hsotg to handle more clocks operation.
Change-Id: I661297ef908d9eace2215205018fa94d12cea128
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
On the rk3288 USB host-only port (the one that's not the OTG-enabled
port) the PHY can get into a bad state when a wakeup is asserted (not
just a wakeup from full system suspend but also a wakeup from
autosuspend).
We can get the PHY out of its bad state by asserting its "port reset",
but unfortunately that seems to assert a reset onto the USB bus so it
could confuse things if we don't actually deenumerate / reenumerate the
device.
We can also get the PHY out of its bad state by fully resetting it using
the reset from the CRU (clock reset unit) in chip, which does a more full
reset. The CRU-based reset appears to actually cause devices on the bus
to be removed and reinserted, which fixes the problem (albeit in a hacky
way).
It's unfortunate that we need to do a full re-enumeration of devices at
wakeup time, but this is better than alternative of letting the bus get
wedged.
Change-Id: I3120a38a7f646a9d244f04bd2dcfef7474a4a6d1
Signed-off-by: Randy Li <ayaka@soulik.info>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(am from https://mail-archive.com/linux-kernel@vger.kernel.org/msg1254059.html)
/tmp/rtl8703b_phycfg-53954c.s: Assembler messages:
/tmp/rtl8703b_phycfg-53954c.s:3071: Error: selected processor does not support `bfc w0,#4,#4'
Change-Id: I9a2cf7ea8b4da82ab6148043983ad57b68b93562
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
drivers/net/wireless/rockchip_wlan/rtl8723cs/core/rtw_debug.c:45:44: error: expansion of date or time macro is not reproducible [-Werror,-Wdate-time]
RTW_PRINT_SEL(sel, "build time: %s %s\n", __DATE__, __TIME__);
Change-Id: I07e50007edc508ec684eb421cfe5fd4378c96553
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This is a HACK patch setting dwc3 dr-mode from otg to peripheral.
Change-Id: I4a6ba065e0369315e95f6ad251b58cc16b1c4e81
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
1 add mclk control
2 add speaker amplifier control
Change-Id: Ib3c03cd281f1ebf4d6d583076bd3930bbe3b3fe0
Signed-off-by: Shunhua Lan <lsh@rock-chips.com>
The driver does not match the dts, pmic driver is update to 4.19 kernel,
but the dts node is not update,make the vcc_ddr regulator init failed:
[ 2.126351] rk808 0-001a: chip id: 0x8160
[ 2.134083] rk808-regulator rk808-regulator: there is no dvs0 gpio
[ 2.134229] rk808-regulator rk808-regulator: there is no dvs1 gpio
[ 2.134347] DCDC_REG1: supplied by vcc_sys
[ 2.136769] DCDC_REG2: supplied by vcc_sys
[ 2.138759] DCDC_REG3: supplied by vcc_sys
[ 2.139064] vcc_ddr: no set_mode operation
[ 2.139110] rk808 0-001a: failed to register 2 regulator
[ 2.140110] rk808-regulator: probe of rk808-regulator failed with error -22
Change-Id: Ieecd8678345202db0be5ac4c669c890283793d42
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
