alignment_init() create proc file "cpu/alignment" at the fs_initcall
level. While "cpu" dir is created on proc_cpu_init() at the same
initcall level too.
Fix this by move alignment_init() to the fs_initcall_sync level.
Change-Id: I8a8831f103b6729f57a8a70ff1bf5672fdf98810
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This option make the kernel boot faster.
Default n.
Change-Id: I918523621044e16953d5611ef9b0f2773746dae9
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
To reduce video node, disable dmaread default.
Define RKISP_DMAREAD_EN to use it.
Change-Id: I26a747e24a1f2f99d62ad986603890499d6cc35d
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
Disable mp/sp link and enable mpfbc default for isp2.0.
Using ispp video to capture image, or disable mpfbc then
to use mp/sp.
Change-Id: I5d21cdaf212cdf77fb3c052e9ad77d1c1166ce0d
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
It contains the arm dbg base addresses.
Change-Id: I245a088d5829b269bb506c145ec6c6f6499258f7
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
1.for bayer raw, do align order
2.sensor can request isp do input crop
3.user can request isp do input crop
Change-Id: I765145f87d38b2610d94118cba6c9b2c31755acc
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
Change 400MHz to 396MHz, 396MHz comes from GPLL, and sometimes HPLL can
be closed
vgg16_maxpool pass.
NPU leakage range: 0.6mA to 1.3mA
0.6mA 0.8mA 0.9mA 1mA 1.1mA 1.2mA 1.3mA
Change-Id: I88edb3e687131b42ed6890153711534bd9f6cc0f
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
According to the hardware test signal, the default drive
strength signal for I2C pins is too strong and changes to
level0 will not.
Change-Id: I8ca50ce3569843f8114fa9bde9bd0d3015cbd218
Signed-off-by: David Wu <david.wu@rock-chips.com>
the regulator-suspend-microvolt of vdd_logic is 725000uV.
the regulator-min-microvolt of vdd_arm is 725000uV
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I3661eda7de740a5d614449e68f556e3c694635a3
If want to use i2c2, we must write i2c2 register bit with 1 at PMUGRF.
Change-Id: Id2b5c1b06c206e43de19fe42024846918fa0b145
Signed-off-by: David Wu <david.wu@rock-chips.com>
Management and enabling of common node more convenient
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Change-Id: Iad15d5cd3a5cc022d41c8c37e051382e82a34217
Based on hardware testing, the level3 signal amplitude
is too strong, and it is enough to drop to the level0 value.
Change-Id: I9ea282f2524449bc81610a45cfd8b1b5e22440e3
Signed-off-by: David Wu <david.wu@rock-chips.com>
These times are all wrong, not real hardware time. For example,
the real rising edge time of i2c0 SCL is about 190ns. In order
to prevent future users from filling in the wrong time, but just
copy, without testing the real time, delete these, and use the
maximum time by default.
Change-Id: I3436b57d9daaeaa8365cb6cf5de7dffbd42db9c9
Signed-off-by: David Wu <david.wu@rock-chips.com>
This patch implements a usb 2.0 phy driver for Rockchip SoCs with
Naneng IP block.
Change-Id: I2658ce7c77a4bef60c8ab183a687d81468a512f1
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
Increase gain size.
Disable sharp dma output if no using.
Change-Id: I0f5bd581bf39b88051b947a34f4ba90cdb789019
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
