Bool type true is exactly BIT(0), so
bool enable = true;
enable &= BIT(2);
enable will be false, which isn't the result we expected in this case.
Change bool type to u32.
The other fix is checking the res in probe() to skip the irq resource.
Change-Id: I2947c9f1e15cb92f03096d26a44759c107bfacd1
Reported-by: Simon <xxm@rock-chips.com>
Suggested-by: Simon <xxm@rock-chips.com>
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
set hdmi phy clock as 148.5Mhz when dclk rate over this frequency
Change-Id: I416b2b98fe42fafc45491b66252f245aed0f1364
Signed-off-by: xuhuicong <xhc@rock-chips.com>
It may caused a dead lock if we flush the hpd work in bridge disable time.
The normal flow would like:
IN --> DRM IOCTL
1. Acquire crtc_ww_class_mutex (DRM IOCTL)
IN --> analogix_dp_bridge
2. Acquire hpd work lock (Flush hpd work)
3. HPD work already in idle, no need to run the work function.
OUT <-- analogix_dp_bridge
OUT <-- DRM IOCTL
The dead lock flow would like:
IN --> DRM IOCTL
1. Acquire crtc_ww_class_mutex (DRM IOCTL)
IN --> analogix_dp_bridge
2. Acquire hpd work lock (Flush hpd work)
IN --> analogix_dp_hotplug
IN --> drm_helper_hpd_irq_event
3. Acquire mode_config lock (This lock already have been acquired in previous step 1)
** Dead Lock Now **
It's wrong to flush the hpd work in bridge->disable time, I guess the
original code just want to ensure the delay work must be finish before
encoder disabled.
The flush work in bridge disable time is try to ensure the HPD event
won't be missed before display card disabled, actually we can take a
fast respond way(interrupt thread) to update DRM HPD event to fix the
delay update and possible dead lock.
(am from https://patchwork.kernel.org/patch/8313001/)
Change-Id: Id7b357de0f497ff8c9f259fe31dc28be34f17083
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Note: Gustavo Padovan try to remove the controller and phy
power on function in bind time at bellow commit:
drm/exynos: do not start enabling DP at bind() phase
But for now driver need to read edid message in .get_modes()
function, so controller must be inited in bind time, so we
need to add controller init back.
(am from https://patchwork.kernel.org/patch/8312921/)
Change-Id: I32abee21665a7e1470f2898b7fbc925108f9d768
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Note: Gustavo Padovan try to remove the controller and phy
power on function in bind time at bellow commit:
drm/exynos: do not start enabling DP at bind() phase
But for now the connector status don't hardcode to connected,
need to operate dp phy in .detect function, so we need to revert
parts if Gustavo Padovan's changes, add phy poweron
function in bind time.
(am from https://patchwork.kernel.org/patch/8312901/)
Change-Id: I0ed1be541210f85883477f1b2a88bd8d57e390d6
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
(am from https://patchwork.kernel.org/patch/8313081/)
Change-Id: If99d29936aafd996c98568d6e184aee6d9c8bc47
Acked-by: Rob Herring <robh@kernel.org>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
(am from https://patchwork.kernel.org/patch/8312881/)
Change-Id: Id1432af874eb0a6dec819d7b7e735c1040f4bf5c
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
(am from https://patchwork.kernel.org/patch/8312861/)
Change-Id: I422216f58a18f2c2fee187b4f19de7b9d0fcd05a
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
(am from https://patchwork.kernel.org/patch/8312841/)
Change-Id: If7a422554ac09cd3ed40eac8191369df532c58bf
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
(am from https://patchwork.kernel.org/patch/8615371/)
Change-Id: Ibe22447ab881b7421e999479cbdfd529d183f6b4
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
After exynos_dp have been split the common IP code into analogix_dp driver,
the analogix_dp driver have deprecated some Samsung platform properties which
could be dynamically parsed from EDID/MODE/DPCD message, so this is an update
for Exynos DTS file for dp-controller.
Beside the backward compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
(am from https://patchwork.kernel.org/patch/8312821/)
Change-Id: I79adafdb4a086d4a357678282cc653a7e3432da9
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
(am from https://patchwork.kernel.org/patch/8312811/)
Change-Id: Ia1d47783b735868a4f56231660d8309cf9c75923
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.
But presumably Exynos still relies on the DT properties, so take
good use of mode_fixup() in to achieve the compatibility hacks.
(am from https://patchwork.kernel.org/patch/8312791/)
Change-Id: Ia7f37daf40fa2d0516d5c44737ad36b5822c6015
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
link_rate and lane_count already configured in analogix_dp_set_link_train(),
so we don't need to config those repeatly after training finished, just
remove them out.
Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets
would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}.
(am from https://patchwork.kernel.org/patch/8312771/)
Change-Id: I8cbf7146d70143bb5d30b3fa971e19f034c30e62
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
In the original split we kept the register constants intact to keep the
diff small. Still the constants are Analogix-specific, so rename them now.
(am from https://patchwork.kernel.org/patch/8312781/)
Change-Id: I714d60bc941b7a992dd34d4c0804576bd07ca84d
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Split the dp core driver from exynos directory to bridge directory,
and rename the core driver to analogix_dp_*, rename the platform
code to exynos_dp.
Beside the new analogix_dp driver would export six hooks.
"analogix_dp_bind()" and "analogix_dp_unbind()"
"analogix_dp_suspned()" and "analogix_dp_resume()"
"analogix_dp_detect()" and "analogix_dp_get_modes()"
The bind/unbind symbols is used for analogix platform driver to connect
with analogix_dp core driver. And the detect/get_modes is used for analogix
platform driver to init the connector.
They reason why connector need register in helper driver is rockchip drm
haven't implement the atomic API, but Exynos drm have implement it, so
there would need two different connector helper functions, that's why we
leave the connector register in helper driver.
(am from https://patchwork.kernel.org/patch/8615401/)
Change-Id: Iad075ae92ba9fa08674fb3d36488f7691909fead
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Commit a9fa852886 ("drm/exynos: dp: add of_graph dt binding support
for panel") made the Exynos DP DT binding more consistent since the OF
graph could be used to lookup either a panel or a bridge device node.
Before that commit, a panel would be looked up using a phandle and a
bridge using the OF graph which made the DT binding not consistent.
But the patch broke the later case since not finding a panel dev node
would cause the driver's to do a probe deferral instead of attempting
to lookup a bridge device node associated with the remote endpoint.
So instead of returning a -EPROBE_DEFER if a panel is not found, check
if there's a bridge and only do a probe deferral if both aren't found.
(cherry picked from commit 37e110625e)
Change-Id: If8b66d792447d4e3455f99dc38b04f334b8b65a6
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Michal Suchanek <hramrach@gmail.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
This patch adds of_graph dt binding support for panel device
and also keeps the backward compatibility.
i.e.,
The dts file for Exynos5800 based peach pi board
has a panel property so we need to keep the backward compatibility.
Changelog v3:
- bind only one of two nodes outbound - panel or bridge.
Changelog v2:
- return -EINVAL if getting a port node failed.
(cherry picked from commit a9fa852886)
Change-Id: Ie300bdc95027269f4a6b0d7fef8d6f0ca4017f06
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Let pm_runtime handle the enabling/disabling of the device with
proper refcnt instead of rely on specific flags to track the enabled
state.
Chnagelog v3:
- revive dpms_mode to keep current dpms mode.
Changelog v2:
- no change
(cherry picked from commit 613d3853c2)
Change-Id: Ieac8db078030f9331135ff0bc43a3a41d56d3b62
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
The DP device will be properly enabled at the enable() call just
after the bind call finishes.
Changelog v2:
- no change
(cherry picked from commit 07c4270302)
Change-Id: Id606cf49e9027036d9c7681b23f39681a3db5e87
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Add a helper that can be used to obtain the number of bits per pixel
corresponding to a given MIPI DSI pixel format. This is useful in
bandwidth calculations, for example.
Change-Id: I03b9f93044ed46a2b999ce82e5623396a6f4d2bc
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
[treding@nvidia.com: add kerneldoc comment and commit message]
Signed-off-by: Thierry Reding <treding@nvidia.com>
(cherry picked from commit ec26d9e938)
There are some IPs, such as video encoder/decoder, contains 2 slave iommus,
one for reading and the other for writing. They share the same irq and
clock with master.
This patch reconstructs to support this case by making them share the same
Page Directory, Page Tables and even the register operations.
That means every instruction to the reading MMU registers would be
duplicated to the writing MMU and vice versa.
Change-Id: I3fd473898274cffcfb46c907b34bd3a4adc29250
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Signed-off-by: Simon <xxm@rock-chips.com>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(cherry picked from commit cd6438c5f8)
This patch replaces ARM-specific IOMMU-based DMA-mapping implementation
with generic IOMMU DMA-mapping code shared with ARM64 architecture. The
side-effect of this change is a switch from bitmap-based IO address space
management to tree-based code. There should be no functional changes
for drivers, which rely on initialization from generic arch_setup_dna_ops()
interface. Code, which used old arm_iommu_* functions must be updated to
new interface.
To avoid build failed on ARCH arm,we mannually fix the following two files that
to use arch_set_dma_ops API
arch/arm/mach-highbank/highbank.c
arch/arm/mach-mvebu/coherency.c
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Conflicts:
arch/arm/mm/dma-mapping.c
Change-Id: Iffad16a7a511d50cc8e422bc61497f117279c66d
Signed-off-by: Simon <xxm@rock-chips.com>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(am from https://patchwork.freedesktop.org/patch/74409/)
This patch moves all the IOMMU-based DMA-mapping code from arch/arm64/mm
to drivers/iommu/dma-iommu-ops.c. This way it can be easily shared with
ARM architecture, which will also use them.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Conflicts:
arch/arm64/mm/dma-mapping.c
Change-Id: I7d56fa5e6e6ef43ae6c9c76035fcf81ee5cb7069
Signed-off-by: Simon <xxm@rock-chips.com>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(am from https://patchwork.freedesktop.org/patch/74408/)
- new method to caculate i2c timings for rk3399:
There was an timing issue about "repeated start" time at the I2C
controller of version0, controller appears to drop SDA at .875x (7/8)
programmed clk high. On version 1 of the controller, the rule(.875x)
isn't enough to meet tSU;STA
requirements on 100k's Standard-mode. To resolve this issue,
sda_update_config, start_setup_config and stop_setup_config for I2C
timing information are added, new rules are designed to calculate
the timing information at new v1.
- pclk and function clk are separated at rk3399.
- support i2c highspeed mode: 1.7MHz for rk3399
Change-Id: I413455cf94fe7486c40694059e2f0931433992bb
Signed-off-by: David Wu <david.wu@rock-chips.com>
