Remove thread init if using DWC_PCIE_PMU,
because late pcie bus scanning would miss probing from dwc_pcie_pmu_init().
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ia27ee055aa3e63deeb7fd646411c3542b7019288
This commit adds the PCIe Performance Monitoring Unit (PMU) driver support
for T-Head Yitian SoC chip. Yitian is based on the Synopsys PCI Express
Core controller IP which provides statistics feature. The PMU is a PCIe
configuration space register block provided by each PCIe Root Port in a
Vendor-Specific Extended Capability named RAS D.E.S (Debug, Error
injection, and Statistics).
To facilitate collection of statistics the controller provides the
following two features for each Root Port:
- one 64-bit counter for Time Based Analysis (RX/TX data throughput and
time spent in each low-power LTSSM state) and
- one 32-bit counter for Event Counting (error and non-error events for
a specified lane)
Note: There is no interrupt for counter overflow.
This driver adds PMU devices for each PCIe Root Port. And the PMU device is
named based the BDF of Root Port. For example,
30:03.0 PCI bridge: Device 1ded:8000 (rev 01)
the PMU device name for this Root Port is dwc_rootport_3018.
Example usage of counting PCIe RX TLP data payload (Units of bytes)::
$# perf stat -a -e dwc_rootport_3018/Rx_PCIe_TLP_Data_Payload/
average RX bandwidth can be calculated like this:
PCIe TX Bandwidth = Rx_PCIe_TLP_Data_Payload / Measure_Time_Window
Signed-off-by: Shuai Xue <xueshuai@linux.alibaba.com>
Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Yicong Yang <yangyicong@hisilicon.com>
Reviewed-and-tested-by: Ilkka Koskinen <ilkka@os.amperecomputing.com>
Link: https://lore.kernel.org/r/20231208025652.87192-5-xueshuai@linux.alibaba.com
[will: Fix sparse error due to use of uninitialised 'vsec' symbol in
dwc_pcie_match_des_cap()]
Signed-off-by: Will Deacon <will@kernel.org>
(cherry-picked from af9597adc2f1e3609c67c9792a2469bb64e43ae9)
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I470f4dc2791168760517c77dd31a4dacd7dab591
Speed change is set via dw_pcie_setup_rc(), so if both of links
support gen2 or gen3, auto speed change will happen. However, if
it's not, provide a manual speed change for EP function driver.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ib0dc765452aef0723968c5d48b5b44de24ca141e
The GPIO1_C5 is multiplexed by VO_LCDC_D6, which needed by
bt1120/bt656/mcu/rgb, and USB20_OTG0_VBUSDET.
Enabling rockchip,vbus-always-on can make ADB work well without
the vbus detection pin.
Change-Id: I7fa705436cf8a1e41f0f61f4941c24f3d9f433b0
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The default hardware design of rk3506g-iotest does not support
USB VBUS detect, so add vbus-always-on property for u2phy.
Change-Id: I9a1a130333a1843335cf2e28c6b705197f086456
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Sync the cma size with mipi display board. It is needed to allocate
22MB cma to meet the rockit application requirements for rk3506.
Change-Id: I94005a69e17f9d0d6aaedee271ba507cc9596ea8
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
1 diff isp version iqtool copy buffer use the same function
2 iqtool before memcpy sync src_buf cache
Signed-off-by: Mingwei Yan <mingwei.yan@rock-chips.com>
Change-Id: I969481c3a59fbff6ec621402e4b19d1647345fde
The following errors are seen when wifi is running:
NOHZ tick-stop error: Non-RCU local softirq work is pending, handler #08!!!
Fix this problem by adding the BH locking around __napi_schedule, in the same way
it was done in commit e63052a5dd ("mlx5e: add add missing BH locking around napi_schdule()").
Change-Id: I25544b52460639ba95d3cbdd9644ab95f01a2654
Signed-off-by: Wenping Zhang <wenping.zhang@rock-chips.com>
Fix the if condition logic in the rockchip_asrc_get_clk_parent
function by replacing the third "&&" with "||".
Change-Id: Ib5c00812bb72c0443ea9565e8d669f7a7fafd156
Signed-off-by: Zhong Shengquan <shengquan.zhong@rock-chips.com>
1. enable sai1 for TDM card
2. enable sai2 for BT card
3. enable sai4 for FA caard
4. enable spidev0.0 for audio control
Change-Id: Ib9a20936164d5ce5d82ba1736001c66eeaaa8b68
Signed-off-by: Zheng zhiqi <looper.zheng@rock-chips.com>
Check whether ipi/link/vid clk is enabled in
uboot to determine whether the uboot logo is
enabled.
Change-Id: I6da4b0694a3df5a48136c96fa21d5f98dcc8d7c7
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Fixes: 73d255eb3b ("nvmem: rockchip-otp: do not close common clk")
Change-Id: I7b73ac1e87bcdab04471eb8805f58fc6a438d7a4
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Fixes: 73d255eb3b ("nvmem: rockchip-otp: do not close common clk")
Change-Id: I719526a754bebbc705c6e283d014e8a7000de3ca
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Fixes: 73d255eb3b ("nvmem: rockchip-otp: do not close common clk")
Change-Id: I470ec453b67aca985dc04f31897ccab86f12d8ad
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Current code if the device is connected and do _dwc2_hcd_resume(),
it will goto unlock and exit this function, cause some dwc2
controllers that does not support Partial Power Down mode resume
failed and perform the following error log:
usb 2-1: reset high-speed USB device number 2 using dwc2
usb 2-1: device descriptor read/64, error -110
usb 2-1: device descriptor read/64, error -110
Fixes: c74c26f6e3 ("usb: dwc2: Fix partial power down exiting by
system resume")
Change-Id: I34d449f1286c8122883aedcd830f2744f1a2267d
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Fix the issue where the system will reboot when exporting the PHY
registers from user space through the following command:
cat /d/regmap/feda0000.phy-dcphy/registers
or
cat /d/regmap/fedb0000.phy-dcphy/registers
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I46f90a04d15a4e583238e966953bc70fb9c3c150
When the amount of data written increases, more space is allocated,
but when the amount of data written decreases, the allocated space
is reclaimed without updating the value of free_size.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Iecf2af482c1e8af35b9fa3227bcbb597d75f770d
Since the hardware bug of HUSB311, its TX fifo become abnormal
when plug in a PD charger after plug out the cable from the PC.
As a workaround, we do ResetTransmitBuffer after each TX packet
is finished to prepare for the next.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: Ieebd090879a45ee2b5a1720e3debf860712e162c
At split mode or dual connector split, the mode of horizontal direction
must x2.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I4583cb575c6714796b63c3dc312eb3c23319b116
