The original pipe_phystatus reg configuration only
set the bit[3:2] (GRF control usb pipe phystatus)
for usb2.0 only interface. It's effective for usb2
device, but it's imperfect for usb2 host mode. In
order to support usb2 host mode, this patch sets
the whole bit[15:0] which include disable u3 port
and select utmi source clock.
Change-Id: I5cde52da2c6e170885df6c4a59f6785e1c485df7
Signed-off-by: William Wu <william.wu@rock-chips.com>
If the uboot logo is enabled, it is needs to obtain the pll frequency
set in the uboot during phy probe. If uboot logo is disabled, it is
need to set a default frequency when enable hdmiphy pll for the first
time.
Change-Id: I566d361a4864324ef4071d9764d84a0fde7d88ee
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Fix bug:
There is a hw bug, the encoder has probabilistically encodes
one frame repeatedlly and does not return enc done in time.
Solution:
Through special config and check the slice done interrupt can determine
that encoding is done and safe reset the rkvenc.
Change-Id: I1a3511523636eac94a9cf89b15cb95b87c447154
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
The default 2-div autocs of vop will cause display abnormal when
multi-pannel with high resolution, so set default div to 1 and
vop driver will take over later.
Signed-off-by: Liang Chen <cl@rock-chips.com>
Change-Id: I6ab9db00ea2cacfdecdb167b7ad67063c25108b1
The power domain of the usb grf belongs to PD_USB
on both RK3576 and RK3588 platforms. The PD_USB is
managed by the USB controller driver, and it maybe
powered down if USB is not working.
Test on RK3576 EVB2 which supports Type-A USB3.1 +
DP 2xLanes, connect DP to Display screen, meanwhile,
USB not used, SError happens with the following log:
[ 224.958079][ C0] Kernel panic - not syncing: Asynchronous SError Interrupt
[ 224.958084][ C0] CPU: 0 PID: 132 Comm: kworker/0:2 Tainted: G O 6.1.57 #11
[ 224.958089][ C0] Hardware name: Rockchip RK3576 EVB2 V10 Android Board (DT)
[ 224.958092][ C0] Workqueue: events dw_dp_hpd_work
[ 224.958101][ C0] Call trace:
[ 224.958103][ C0] dump_backtrace+0xf4/0x114
[ 224.958115][ C0] show_stack+0x18/0x24
[ 224.958122][ C0] dump_stack_lvl+0x6c/0x90
[ 224.958132][ C0] dump_stack+0x18/0x38
[ 224.958137][ C0] panic+0x14c/0x338
[ 224.958145][ C0] check_panic_on_warn+0x0/0x90
[ 224.958155][ C0] arm64_serror_panic+0x68/0x74
[ 224.958160][ C0] do_serror+0xc4/0xcc
...
[ 224.958218][ C0] regmap_write+0x54/0x78
[ 224.958224][ C0] udphy_power_on+0x16c/0x1b0
[ 224.958233][ C0] rockchip_dp_phy_power_on+0x58/0x1bc
[ 224.958240][ C0] phy_power_on+0x8c/0x108
[ 224.958248][ C0] dw_dp_bridge_detect+0x58/0x348
[ 224.958256][ C0] drm_bridge_detect+0x28/0x34
[ 224.958264][ C0] dw_dp_connector_detect+0x34/0x4c
[ 224.958272][ C0] drm_helper_probe_detect+0xd0/0x1a0
[ 224.958281][ C0] check_connector_changed+0x50/0x1b0
[ 224.958288][ C0] drm_helper_hpd_irq_event+0x78/0x134
[ 224.958295][ C0] dw_dp_hpd_work+0x58/0x818
This patch moves udphy_u3_port_disable() from the
udphy_power_on() to rockchip_u3phy_init(), it can
avoid access usb grf during dp phy power on, and
the rockchip_u3phy_init() is called from the USB
controller driver, this can make sure the PD_USB
is powered on if it access usb grf in the USBDP
PHY driver.
Change-Id: I434b2efbbbb5b513ec668bca1c8800d0f7f18e12
Signed-off-by: William Wu <william.wu@rock-chips.com>
Detecting the hpd irq in the gpio irq handler, the hpd
type will overwrite by the next gpio irq. So the hpd work
can't recognize the hpd irq.
Use a state machine to deal with the hpd status to avoid this
issue happen.
Change-Id: I1214b1a281cbb8e82431bcc1c2b4a0856d64a7a0
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
set vop aclk mode to ROCKCHIP_VOP_ACLK_RESET_MODE is better
for power and performance.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I8514e57af6ac8950112a6c675f5eb03fe4e44cf0
The VOP Lite unit is found on rk3576 which use legacy VOP architecture.
Change-Id: I800523a7dac1e086db26b3fbf731f3d07e1ed68d
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
To save mcr value when uart is reset for setting baudrate.
Change-Id: I1a4fcd78498cf4f601d0c8461d1db67dc0ed6f9e
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
The wrong value will make irq counter stop to increase at 200001, and
software takes more time to finish encoding.
Fixes: 53048fad2a ("video: rockchip: mpp: Add JPEG VPU720 driver")
Signed-off-by: Johnson Ding <johnson.ding@rock-chips.com>
Change-Id: Id98fcdc6d4e617e8dfba1bc6471295a14c48594b
VOP YUV overlay only can support YUV limit range, so force select BT601L
todo R2Y.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I3af0d916d549a1fd890f14d3723f3264c779a1ea
Plane csc determines its own color input path on the input
color format of plane. So when DCI is enabled should force
yuv csc path.
Change-Id: I66d5f3e773fc0fd631673622c22b242dcc791afe
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
1.Delete the assigned-clock
2.Only rely on spi-max-frequency configuration in sub nodes
Change-Id: I040a3afaa0c92de854f9f21eb58e912d6638b080
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
1.Delete the assigned-clock
2.Only rely on spi-max-frequency configuration in sub nodes
Change-Id: I952376e0e898635dda299c833759a84efbe631cf
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
1.Delete the assigned-clock
2.Only rely on spi-max-frequency configuration in sub nodes
Change-Id: Idb3f0d243faf72659e81416063a920401c1e13b7
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
1.Delete the assigned-clock
2.Only rely on spi-max-frequency configuration in sub nodes
Change-Id: I481d1c6ffeb2f7f70fe7a8a8cf1a633319a0b4bd
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
1.Delete the assigned-clock
2.Only rely on spi-max-frequency configuration in sub nodes
Change-Id: Ia8961e12ef5f6812ac12de1b6fdfdb5f6bda8267
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Some device DPCD Reversion is 1.2, but It can't write
Ainfo register REAUTHENTICATION_ENABLE_IRQ_HPD bit. For there
devices, it should avoid write REAUTHENTICATION_ENABLE_IRQ_HPD
bit.
It better to write REAUTHENTICATION_ENABLE_IRQ_HPD bit to Ainfo
register just when the DPCE Reversion higher than 1.2.
Change-Id: I10dcae33e8f33c9d41a05752caebc9cd085e729b
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
In DisplayPort HDCP1.3 Spec Section 2.2.2 page 12, It
indicate that the maximum-permitted time to receive ready
status bit is 5s for repeater.
Change-Id: I5a01c742328c2c6dfbd49fa31f952ab5b858fee0
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
In DisplayPort HDCP1.3 CTS case 1A-01 page 10, unencrypted video
signal should be sent before enable hdcp.
In DisplayPort HDCP2.2 CTS case 1A-1 page 12, unencrypted video
signal may be sent before enable hdcp.
Change-Id: I12f5ec4143728683663cba5a0f079c915c500383
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
The benchmark test shows a significant score drop from 87038 to 73764,
if enabling UFSHCD_CAP_RPM_AUTOSUSPEND, due to the slow recover process
during readom rw test.
Meanwhile we finally have a power consumption result, which shows even more power
consumption was observed due to the phy/unipro status mismatch, one side is in H8,
another side lost the link.
|scene | UFS 128G rpm disable |UFS 128G rpm enable |
|-------------------------------------------------------------------------------------|
|screen 3.8V |TEMP25 |DDR |V |mA |VBAT |V |mA |VBAT |
|-------------------------------------------------------------------------------------|
|Static Desk |36 |528 |3.8V |419.11 |3.845|414.2 |3.8V |418.79 |3.843|414.1|
|-------------------------------------------------------------------------------------|
|Static Desk[1]|36 |528 |3.8V |125.76 |3.882|123.1 |3.8V |127.05 |3.881|124.4|
|-------------------------------------------------------------------------------------|
|1080P video |36 |528 |3.8V |556.83 |3.827|552.9 |3.8V |584.63 |3.829|580.2|
|-------------------------------------------------------------------------------------|
|1080P video[2]|36 |528 |3.8V |525.06 |3.837|520 |3.8V |499.98 |3.839|494.9|
|-------------------------------------------------------------------------------------|
|Note: [1] no screen [2] no buffering |
|-------------------------------------------------------------------------------------|
Moreover it significantly increases the possibility of failing to wait UIC ready state,
which can lead to very long reset and restore link process, adding more latency to the
system.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I9839fdb4a93c0ecae4b581f07db3281a40a2fa25
The PWM io input/output state is controlled by PWM mode
configuration. In order to avoid the antagonistic drive
state between the PWM pin and the external pin, keep the
PWM mode fixed in capture mode although PWM is disabled.
Change-Id: I6183987c9bef6f444726643f878c5384f63844d0
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
drivers/gpu/drm/rockchip/rockchip_drm_vop.c:2386: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* rockchip_atomic_helper_update_plane copy from drm_atomic_helper_update_plane
drivers/gpu/drm/rockchip/rockchip_drm_vop.c:2386: warning: missing initial short description on line:
drivers/gpu/drm/rockchip/rockchip_drm_vop.c:2458: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* drm_atomic_helper_disable_plane copy from drm_atomic_helper_disable_plane
drivers/gpu/drm/rockchip/rockchip_drm_vop.c:2458: warning: missing initial short description on line:
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ie9d2e00238e4c45d6a8ad7581ea7482b14092a23
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c:6139: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c:6210: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I24f65edf0c4900c09d5b68411a8f2dd473260ce6
