Commit 6de4caa7df ("arm64: dts: rockchip: rk356x-evb: fix pcie supply
to regulator-fixed") cleanup these stuff but we still have some left.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I29ebb92cc3dd0eaccfa610c7d526e46a0c33f320
This patch place parentheses around 'x' to silence potential warning.
Change-Id: I7c6cd70c03f71e85bd39faa092f2d0eb61409431
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
When do charge detection, the phy specification suggests that
it needs to holds the phy in reset state to avoid USB data
communication. However, the utmi clk60_30 will be disabled at
the same time, that's causing a synchronization issue between
the phy and the USB controller.
I test on RV1126 EVB Linux SDK, do usb device hot plug test
quickly. The USB dwc3 controller may fail to enable ep0 because
of no clk60_30 is supplied by the phy.
This patch sets the phy utmi in normal mode by GRF to keeps the
utmi clk on for USB controller.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I8958a491130faeb9ac361b8639e4c3d3190fad1b
When the related print appears, it means that the SDK is too old
and the storage driver needs to be updated.
Change-Id: I63f45fba4cf52108c628f225ee23aa0819ca256f
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
make sure vop power is enabled before use priv function crtc_close() to
close current crtc plane.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I928e5f0f38692fbb8a134e6938ec28f8c1f41285
overlay mode: black and white use du framecount,
to fix trailing smear when draw line on grey background
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
Change-Id: If02bd8edb0c02a159a5359a231b487b09dfd26d2
When area0 is disabled, all other sub multi area must be
disabled, or the win may run into unexpected situlation:
such as post_buf_empty or iommu fault.
Change-Id: I8a92e45849cfc31af029ba0e86562751be92ddbd
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
HDR window is fixed(not move in the overlay path with port_mux change)
and is the most slow window. And the bg is the fast. So other windows
and bg need to add delay number to keep align with the most slow window.
The delay number list in the trm is a relative value for port_mux set at
last level.
Change-Id: I731b909c0a3f483be081e16610536b4ce5b9b8b0
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
DPTX implements the programmable SSC down-spreading with up to
0.5% modulation amplitude and 30k/33k modulation frequency.
Change-Id: I2c3eae8f27c84eb1b22eac8973691e0276c1588e
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
ddr clk using SCMI that it no longer need sclk_ddrc.
Change-Id: I5cee84896083610d9b1a5bc6bcd23ac628ec5c73
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Add rockchip_ddr_set_rate to support ddr frequency switching.
This function wraps the SMC call and frequency switching is
implemented in ATF. Afterwards it will call clk_get_rate to
update the rate in clock framework.
Set dmcfreq->is_set_rate_in_dmc=true to enable this process.
Change-Id: I9349a2e8413751360bf105a70e46d1453791194c
Signed-off-by: YouMin Chen <cym@rock-chips.com>
"system-status-level" property define only frequency level, not the
actual frequency. In dmc driver, it will switch from frequency level
to actual frequency base on available frequencies table which get
from ATF.
Change-Id: I489b671da5e56912d4f970d32174bdc8b1f86a08
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Add the function of rockchip_get_freq_info to get available ddr
frequencies info via SMC call. The frequency info include available
frequencies count and frequencies table(sort by rate from low to high).
Afterwards it will update the dmc_opp_table base on frequencies info.
If have "system-status-level" property in dmc, the function of
rockchip_get_system_status_level will get the frequency for
system-status base on frequency level and available frequencies table.
Change-Id: I73d0f999e718ba9426ad75e48ac2a4ec3fe5f496
Signed-off-by: YouMin Chen <cym@rock-chips.com>
rockchip pcm is a wrapper of snd dmaengine pcm with customize
config, to achieve flexible config.
Change-Id: I3a4f4571962fb694814173db294891d842749983
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
rockchip pcm is a wrapper of snd dmaengine pcm with customize
config, to achieve flexible config.
Change-Id: I35c8058c929c9e23992010655e2f9b7bc49f632d
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
rockchip pcm is a wrapper of snd dmaengine pcm with customize
config, to achieve flexible config.
Change-Id: I01ffe93ed90700cb0634a8b53d5fe044c0415f00
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
rockchip pcm is a wrapper of snd dmaengine pcm with customize
config, to achieve flexible config.
Change-Id: Ie073d9e94c740fec5b0d398ccd3e212af7fba519
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
rockchip pcm is a wrapper of snd dmaengine pcm with customize
config, to achieve flexible config.
Change-Id: I164e22dc3716075ccd520b74f03f554c075f25ec
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This patch make rockchip_pcm.c compiled depends on SND_SOC_ROCKCHIP,
because all the dai of rockchip will switch to use it, and we can
do much more customize, such as minimize the prealloc buffer size.
Change-Id: Ia7a3923db6760273d2291b41c194f28b43de83b2
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
1.improve buf manager to aovid memleak and buf lost
2.don't refresh overlay image when overlay disabled
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
Change-Id: Ib3ef89752549cf89230827ed91440b831a0544e2
The CLK_SET_RATE_PARENT flag make the parent clock and the child clk is 1:1.
If the DCLK frequency is too low, the PLL frequency will be very
low, which will affect the output waveform quality of PLL, and PLL
locking may be abnormal, so add a new COMPOSITE_DCLK clock-type to
handle that.
Change-Id: Id95a14c0fbd0ad2799a77190a5d21dd490c6ede8
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
1.full/a2/du/du4: check part also
2.auto mode use full gc16 waveform to reduce ghosting
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
Change-Id: I3a2156ccecc5d630b1adb2425d647fb8efb090be
Add CLK_GATE_NO_SET_RATE for gate clks not allowed to support setting
rate.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Iddd1c958661f8ff9217b8781426314b0619367db
The maximum alpha is 255, but after the product of color and alpha
in the blend formula, the final result is >> 8 (/256) instead of
/255, which will introduce errors.
This fix is that when alpha is 0x80~0xff, then +1.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: Ibba964f29a11eb226aa008a0dd5bf89048524b43
