The user can update the dimming data via "DIMMING_DATA" property, and
it will be sent to the panel supported local dimming function in the
rockchip dimming panel driver.
Change-Id: I7dba541450fce86be064d0205af0f595b1712aea
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
In order to support the loader protect function of more panel
drivers, we add the DRM panel as part of Rockchip DRM sub devices.
The panel-simple driver always is regarded as a panel driver demo of
Rockchip platforms, so we first add the Rockchip DRM sub_dev for it.
The panel drivers that adapt to Rockchip DRM drivers can call
rockchip_drm_register_sub_dev()/rockchip_drm_unregister_sub_dev() to
register/unregister DRM sub_dev, and then invoke
rockchip_drm_panel_loader_protect() to achieve the panel loader
protect function.
Change-Id: Ibc302c3f3677e0c55545e90af29d7a87444c2e21
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
In order to enhance the flexibility of loader protect callback
&rockchip_drm_sub_dev.loader_protect(), we replace the parameter
'struct drm_encoder *encoder' by 'struct rockchip_drm_sub_dev'so that
the panel or bridge drivers can apply it to achieve the loader
protect function.
Change-Id: Ic26110583245c1a0807fee35f4dd889ee8f1f845
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
In the past, the flag &rockchip_pwm_chip.oneshot_en may not represent
the accurate enabled status for oneshot mode, because the oneshot mode
should be active after setting the 'pwm_en' bit. Therefore, we add the
&rockchip_pwm_chip.oneshot_valid to represent the validity of oneshot
configurations, and &rockchip_pwm_chip.oneshot_en does what it should
do.
In addition, the disabling of oneshot mode does not need to delay one
period(related commit 42e759004f ("pwm: rockchip: add one period
delay before disabling the dclk")). It will end after the last period
sent.
What's more serious, the disabling process may be done in interrupt
handler for oneshot mode(The handler is flexible for user as designed),
so it is unreasonable to call fsleep() in the interrupt handler, which
may cause the following error with 100000ns period:
[ 6.517981] BUG: scheduling while atomic: swapper/0/0/0x00010000
[ 6.518045] Modules linked in:
[ 6.518060] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 6.1.118 #944
[ 6.518069] Hardware name: Rockchip RK3576 EVB1 V10 Board (DT)
[ 6.518078] Call trace:
[ 6.518085] dump_backtrace+0xd8/0x130
[ 6.518108] show_stack+0x1c/0x30
[ 6.518118] dump_stack_lvl+0x64/0x7c
[ 6.518132] dump_stack+0x14/0x2c
[ 6.518141] __schedule_bug+0x58/0x70
[ 6.518155] __schedule+0x6f0/0x7c0
[ 6.518164] schedule+0x54/0xe0
[ 6.518172] schedule_hrtimeout_range_clock+0xa8/0x144
[ 6.518184] schedule_hrtimeout_range+0x18/0x20
[ 6.518193] usleep_range_state+0x7c/0xb0
[ 6.518204] rockchip_pwm_enable_v4+0xc8/0x104
[ 6.518219] rockchip_pwm_apply+0x80/0x190
[ 6.518229] pwm_apply_state+0x68/0x190
[ 6.518239] rockchip_pwm_irq_v4+0x7c/0x1b0
[ 6.518250] __handle_irq_event_percpu+0x58/0x1d0
[ 6.518265] handle_irq_event+0x4c/0x110
[ 6.518276] handle_fasteoi_irq+0xc0/0x24c
[ 6.518290] generic_handle_domain_irq+0x30/0x44
[ 6.518302] gic_handle_irq+0x60/0x90
[ 6.518312] call_on_irq_stack+0x24/0x34
[ 6.518323] do_interrupt_handler+0x80/0x94
[ 6.518333] el1_interrupt+0x44/0xa0
[ 6.518345] el1h_64_irq_handler+0x14/0x20
[ 6.518357] el1h_64_irq+0x74/0x78
[ 6.518366] cpuidle_enter_state+0xbc/0x434
[ 6.518382] cpuidle_enter+0x3c/0x50
[ 6.518393] do_idle+0x228/0x2b0
[ 6.518405] cpu_startup_entry+0x38/0x40
[ 6.518416] kernel_init+0x0/0x12c
[ 6.518425] arch_post_acpi_subsys_init+0x0/0x18
[ 6.518439] start_kernel+0x6b0/0x6ec
[ 6.518450] __primary_switched+0xb4/0xbc
This patch will also help to avoid the above abnormal situation.
Change-Id: I0df715921d79803f06329a71b966a4ae40876f33
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Fixes: 42e759004f ("pwm: rockchip: add one period delay before disabling the dclk")
Change-Id: I612fde2adf60940e17146a115a104caf302109b2
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Disable async probe if CONFIG_TOUCHSCREEN_HYN is enabled, since the EVB
requires sequential probing of both gt1x and hyn touchscreen drivers.
Type: Function
Redmine ID: #N/A
Associated modifications: N/A
Test: N/A
Signed-off-by: Zhibin Huang <zhibin.huang@rock-chips.com>
Change-Id: I4610e82d478aa328c0459bec8e9ce270644e3a1b
When uboot logo is enabled, we think it has completed the link training
in the uboot stage. so the cr done and eq done flag should be config.
And the retraining will not be filter.
Change-Id: Ibb68c3c6f42837568143f856c9f68fb8f882969a
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
In some case, the color depth will be 8bit when output
hdr content. So it need limit coor depth as 8bit for
hdr.
Change-Id: I7415230d4e0c4c08097ea5912aff791875db6176
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
The cif/isp depend on iommu, it's appropriate to set the one grader lower level.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: Ie25e1ecafffff342b2a726cdc770ea6a90c10736
The csi2-dphy depends on csi2-dphy-hw, assign different levels to them.
No need to pay attention to INITCALL_ASYNC.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: Ieda3c7737c4e07af3d9664ceee8868ba55dbefbe
reserved plane mode will enable iommu bypass for rtos reserved plane
display, but rkiommu 2.0 can't support iommu bypass function, so use
rkiommu 1.0 at reserved plane mode by default, others will use rkiommu
2.0 by default.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I68f2ae66e4e0d7eec45264c39a7f23deab01c8eb
reserved plane display will be enabled as following config at dts,
then the reserved plane will be update by other OS, and the reverved
plane zpos is always at the top of other planes.
example:
&vp1 {
rockchip,drm-fbd-mode = <ROCKCHIP_DRM_FBD_FROM_RTOS>;
rockchip,reserved-plane = <ROCKCHIP_VOP2_ESMART1>;
};
If userspace want to exit from reserved plane, you can set the property:
RESERVED_PLANE_MASK to 0, and the reverved plane will become the
normal plane.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I34e7a7470e2f6685aea5a228b58bdb84eb9c1e92
Note: multiple raw sensor link to isp depend on config MULTI_RAW_SENSOR_LINK_TO_ISP
Signed-off-by: Cai Wenzhong <cwz@rock-chips.com>
Change-Id: I700fcc8b94b0c993b125ca8cba60f1148f38900f
