Writing reg 0x300 BIT(31) may cause the DMA module to falsely
trigger writing data. It will case enc err.
So we need to disable the core clock before writing reg 0x300,
and re-enable the core clock after writing reg 0x300.
Change-Id: Ib385b3aa120533cd42b70b548120d219ceaf4fb5
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
The original on/off hdcp process will cause hdmi and vop to be on/off,
which will affect other display interfaces in the mirror scenario.
Change-Id: I1f83063e800beb0b78cd793971e5f4f65b8bf55e
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
The parent clock of PCLK_HDPTX_APB is PCLK_PMUPHY_ROOT,
which must be always on.
In order to reduce power consumption, replace apb clock
PCLK_PMUPHY_ROOT by controllable PCLK_HDPTX_APB in
suspending and resuming.
Change-Id: I1103b9bf542bacfd021de9a2553265fd6960e6d5
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
This patch supports select and swap ADC data, the item
'Left Right' is default.
For example, swap left and right for ADC:
----
amixer -c 0 sset 'ADC Data Select' 'Right Left'
Simple mixer control 'ADC Data Select',0
Capabilities: enum
Items: 'Left Right' 'Left Left' 'Right Right' 'Right Left'
Item0: 'Right Left'
Change-Id: Ied9296929010e93773cf335f210c3ec7be12481e
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
For RK3576 VP0 enable ACM[set acm bypass from 1 to 0] must at standby mode, otherwise
will lead to timing error, so we enable ACM by default.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I7711cd0ca5b56c3a7bfef800bf9e61a5c0697e90
Generally speaking, the codec needs to ensure the normal
input of left and right channels independently. If you
want to forcethe duplication of channels, you can configure
it through the control node in the user layer.
Enabling ALC NG here will cause the sound pickup effect
to be unstable.
And, the default public version does not need to turn on
the ALC NG function, so as not to introduce non-linear
processing to the backend algorithm and cause unnecessary
confusion to developers.
Change-Id: I52e376c7d992d4bd08e863134b4c596cbfccbe2b
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
ciu clock from CRU is 2 times of interface clock, so the delay number
maybe not so accurate as the sample phase is based on interface clock.
Change-Id: Ib8d66f1c7af18fa3888dafc4528a95aabfa8572f
Fixes: 1505eda5b9 ("mmc: dw_mmc-rockchip: Add internal phase support")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
The parent clock of PCLK_HDPTX_APB is PCLK_PMUPHY_ROOT,
which must be always on.
In order to reduce power consumption, replace apb clock
PCLK_PMUPHY_ROOT by controllable PCLK_HDPTX_APB in
suspend and plug out.
Change-Id: I856fa05382ea50a7541195d49941c113bbe3986a
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
The husb311 driver disable irq wakeup if vbus is on
(e.g connect with an U Disk), it aimed to avoid wakeup
system from deep sleep immediately by husb311 irq if
the vbus was powered off during deep sleep.
However, some platforms can keep vbus on during deep
sleep, and it may want to support the husb311 irq to
wakeup system from deep sleep, so this patch adds an
option property "wakeup-source" for this scenario.
Fixes: a6a4762e0c ("usb: typec: tcpci_husb311: Refactor irq wakeup")
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I3a862b3b3e99fe12c4dbb87e09a0910b4602b92a
Under the condition of 10K speed, data update point for data hold time
is calculated, which may exceed the maximum value 0x5, and the limit
is added to make its value within a reasonable range.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ic9cc68c172dc8720f6fa0bbc9714ce33ea9dc608
If using the hdmi2dp ext board, eDP uses the hardware
link of HDMI, whose phy is multiplexed with eDP, and
the HDMI controller does not actually work.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Icc70e713799e1fa6eb49e419bae1c96a54e838af
After set pre_scan_hblank minimum value to 8 by the following commit,
the aclk and dclk must meet as: aclk > 1/2 * dclk.
commit ce8f21340f ("drm/rockchip: vop2: set pre_scan_hblank minimum value to 8")
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I4968a29ef0aab4e413990c1b9a406efec067c9d0
For simulation aux client, the virtual channel pyaload id can't
send by sideband MSG. In this case, the MST device often config
a fix payload id. It need DPTX also config fix payload id to
match the MST device.
Change-Id: I49148e92a80091a50a5b1f44496430f39d9c1aee
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
some MST-capable device may not support Messaging AUX Client.
In this case, sideband MSG can't be transferred between DPTX
and the MST device. A solution is to simulate a Messaging AUX
client in MST device side to deal with sideband MSG.
Change-Id: I7c68f6d0bd88501c4e19097e3a1f9a9fabcf2698
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Once upstream is merged, this patch can be dropped.
also for line CONFIG_NO_GKI
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I83f5a08e93010741c26ec044f70b388a50e6c7a9
Once upstream is merged, this patch can be dropped.
also for line CONFIG_NO_GKI
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I2b0fc69aa6673e46dcd65e0369ab4353e7c4f9fc
