The win phy id can be used by dts and vop2 driver, so move them together
at rockchip_vop.h
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I0d6c8d48ba42425ff73d65aef843011d7112d981
RK356x can't support uv swap, so only can support YVYU and VYUY.
Fixes: cf58ab4406 ("drm/rockchip: vop2: rename and correct supported format")
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Iea986580194b4a2aa6ce9943b27b8b3766285502
solved the problem that the fast startup probability is not displayed
Change-Id: Ib65866467dea93955d1b75389d7ef5790c9bc65d
Signed-off-by: Hongming Zou <hongming.zou@rock-chips.com>
Add bindings for the Rockchip Flexbus controller under SPI mode.
Change-Id: I894bc3f6bcfe62cbe593be2e932bf982aad758fd
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Lane event counter usage in Rockchip is slightly different with
T-Head. Fix it by checking vendor ID.
Fixes: 6cb6a00862 ("perf/dwc_pcie: Add support for Rockchip vendor devices")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Iccc25bb7b352f73bae963d827f14b2f7405608b2
The rockchip,data-swap can help to swap left and right channel
display data in dual channel mode.
Change-Id: I9da870852421e12477027cb74ee01ee9a951c14f
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Since Rockchip's GPIO hardware debounce function does not support
configuring individual pins, it will not be used.
Partially revert commit 2af76b3213 ("gpio: rockchip: Update debounce config function").
Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Change-Id: I3c9fd877643aaac3816181a61052d395c95c6593
During the playback, if PLL_PW_DOWN and PLL_PW_UP is performed,
a POP sound is generated.
When the sample rate does not change, do not restart the pll.
Change-Id: I83de976e6e2752a85c57fbc4d4eb6bd5f1b21fbf
Signed-off-by: Binyuan Lan <lby@rock-chips.com>
RPMSG notify function sends a notification to the remote
side when the ring buffer updated, without needing an
immediate response. The remote side can then process
multiple data packets simultaneously.
Signed-off-by: Zain Wang <wzz@rock-chips.com>
Change-Id: Id1dd2d52e5587c319a8530272fe4fd818b7d1509
Retain tx_msg buffer until mailbox sent data success.
Signed-off-by: Zain Wang <wzz@rock-chips.com>
Change-Id: If37f38aa703702a589a542a897ec7c5b6dd27b92
Add a callback function to tick the sending transmission
when received tx bufs release messages.
Change-Id: Ibe7555daffe2038513fe16f8599326d99ffae650
Signed-off-by: Zain Wang <wzz@rock-chips.com>
Remove thread init if using DWC_PCIE_PMU,
because late pcie bus scanning would miss probing from dwc_pcie_pmu_init().
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ia27ee055aa3e63deeb7fd646411c3542b7019288
This commit adds the PCIe Performance Monitoring Unit (PMU) driver support
for T-Head Yitian SoC chip. Yitian is based on the Synopsys PCI Express
Core controller IP which provides statistics feature. The PMU is a PCIe
configuration space register block provided by each PCIe Root Port in a
Vendor-Specific Extended Capability named RAS D.E.S (Debug, Error
injection, and Statistics).
To facilitate collection of statistics the controller provides the
following two features for each Root Port:
- one 64-bit counter for Time Based Analysis (RX/TX data throughput and
time spent in each low-power LTSSM state) and
- one 32-bit counter for Event Counting (error and non-error events for
a specified lane)
Note: There is no interrupt for counter overflow.
This driver adds PMU devices for each PCIe Root Port. And the PMU device is
named based the BDF of Root Port. For example,
30:03.0 PCI bridge: Device 1ded:8000 (rev 01)
the PMU device name for this Root Port is dwc_rootport_3018.
Example usage of counting PCIe RX TLP data payload (Units of bytes)::
$# perf stat -a -e dwc_rootport_3018/Rx_PCIe_TLP_Data_Payload/
average RX bandwidth can be calculated like this:
PCIe TX Bandwidth = Rx_PCIe_TLP_Data_Payload / Measure_Time_Window
Signed-off-by: Shuai Xue <xueshuai@linux.alibaba.com>
Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Yicong Yang <yangyicong@hisilicon.com>
Reviewed-and-tested-by: Ilkka Koskinen <ilkka@os.amperecomputing.com>
Link: https://lore.kernel.org/r/20231208025652.87192-5-xueshuai@linux.alibaba.com
[will: Fix sparse error due to use of uninitialised 'vsec' symbol in
dwc_pcie_match_des_cap()]
Signed-off-by: Will Deacon <will@kernel.org>
(cherry-picked from af9597adc2f1e3609c67c9792a2469bb64e43ae9)
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I470f4dc2791168760517c77dd31a4dacd7dab591
Speed change is set via dw_pcie_setup_rc(), so if both of links
support gen2 or gen3, auto speed change will happen. However, if
it's not, provide a manual speed change for EP function driver.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ib0dc765452aef0723968c5d48b5b44de24ca141e
The GPIO1_C5 is multiplexed by VO_LCDC_D6, which needed by
bt1120/bt656/mcu/rgb, and USB20_OTG0_VBUSDET.
Enabling rockchip,vbus-always-on can make ADB work well without
the vbus detection pin.
Change-Id: I7fa705436cf8a1e41f0f61f4941c24f3d9f433b0
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The default hardware design of rk3506g-iotest does not support
USB VBUS detect, so add vbus-always-on property for u2phy.
Change-Id: I9a1a130333a1843335cf2e28c6b705197f086456
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
