This patch fix the aloop card index to 7, and leave the card 0
place for default hw snd card.
Change-Id: I767d3d61b1ecb09b813d7bf81b99298cd30a3969
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This patch make the waterlevel more reasonable, because the pdm
controller share the single FIFO(128 entries) with each channel.
adjust waterlevel in frame to meet the vad or dma frames request.
Change-Id: I9b5808e55025347d435f47889f39ba34ac07ea1c
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
fix the vts error like this:
Failed to parse! Parsing error at token LexToken(COMMA,',',1,48) in line 1;
explain:
the vts will parsing the codec'name after android P, the comma is not allow
in the codec'name
Change-Id: I6cb011331368d64417bd9955ba5d3deb84d49b8d
Signed-off-by: Xinhuang Li <buluess.li@rock-chips.com>
On rk3399 platforms, Type-c1 can be simplified to Type-A
port and support USB 3.0 Host only mode. It has a problem
that the dwc3_rockchip_resume() will reset the controller
upon pm resume, and this may cause usb device(e.g. usb 4G
modem) to be reenumerated. This patch sets the flag of
connected to true and avoid to do the reset operation upon
pm resume.
Change-Id: I57f92d0277a19ce1c7b881fe2da6470fd3a70b73
Signed-off-by: William Wu <william.wu@rock-chips.com>
According to the PHY datasheet of rtl8211f, if the reset time
of the PHY is not enough, it will cause the PHY instability,
which has been encountered by other customers, need to take
longer than rtl8211e.
Change-Id: I2786c8b9005a3437d39d6b580d01f03c590848d6
Signed-off-by: David Wu <david.wu@rock-chips.com>
Make of_devfreq_cooling_register_power() as static inline.
This fixes the building error when CONFIG_THERMAL is disabled.
Change-Id: I3d88a3679de279a7ee7eadae7243b9661fdddf75
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
In some case，log like this:
[ 12.393926] rk3x-i2c ff150000.i2c: irq in STATE_IDLE, ipd = 0x51
[ 12.416592] rk3x-i2c ff150000.i2c: irq in STATE_IDLE, ipd = 0x51
The i2c clock is disabled, so the pending irq clean is not
worked. Disable the interrupt after the i2c jobs were done,
the error log would not happen.
Change-Id: If04a2e2214d675410c67db0f131ee7ef635ddcb4
Signed-off-by: David Wu <david.wu@rock-chips.com>
If the slave hold the scl low for a long time, we will send
the stop because the i2c transfer is timeout. Then reset the
slave, the scl will be released to high by slave, the data
hold low, but the controller's state is messy now, need to
diable i2c controller, it is better to reset i2c controller,
it will go back to normal state.
The log like this:
[ 117.444700] rk3x-i2c ff3d0000.i2c: timeout, ipd: 0x93, state: 2
[ 118.466410] rk3x-i2c ff3d0000.i2c: timeout, ipd: 0x00, state: 1
[ 119.486217] rk3x-i2c ff3d0000.i2c: timeout, ipd: 0x00, state: 1
or
[ 91.733176] rk3x-i2c ff3d0000.i2c: timeout, ipd: 0x80, state: 1
[ 103.406776] rk3x-i2c ff3d0000.i2c: timeout, ipd: 0x00, state: 2
[ 104.426636] rk3x-i2c ff3d0000.i2c: timeout, ipd: 0x00, state: 2
Change-Id: I53e6e383c849cea22d870f9488c23720e74115df
Signed-off-by: David Wu <david.wu@rock-chips.com>
Add a quirk to avoid USB 3.0 PHY enter suspend mode when
the dwc3 controller suspend conditions are valid, it can
help to fix the dwc3 initialization error issue with the
following log:
dwc3 fd000000.dwc3: failed to enable ep0out
Change-Id: Iedcb9fa6c2c7fe923839362e35267fedb55889a7
Signed-off-by: William Wu <william.wu@rock-chips.com>
Add otg vbus regulator for rk1808 evb, it can provide
5V power supply for otg host.
Change-Id: Ib535993d5446c7fbf58e58ab748e8d565f81447f
Signed-off-by: William Wu <william.wu@rock-chips.com>
The combphy which supports PCIe/USB3.0 on rk1808 has been
enabled, so we can used it as usb3-phy for DWC3 controller
by default.
Change-Id: I106885eb79621b40214bc2ebac43d8f87ac63687
Signed-off-by: William Wu <william.wu@rock-chips.com>
The default clock frequency of usb3 suspend_clk is
32KHz, this patch sets the clock frequency to 24MHz
which from the xin24m parent.
Change-Id: Ia516a0d7b6c69b87a1ad6c69c421504477e18742
Signed-off-by: William Wu <william.wu@rock-chips.com>
Add combphy node for rk1808, this phy can be used
as pcie-phy or usb3-phy.
Change-Id: Idddeabf32a21560ad134ff9cc0a9a3f406f8d1a7
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch implements a combo phy driver for Rockchip SoCs
with Innosilicon IP block. This phy can be used as pcie-phy,
or usb3-phy.
Change-Id: Id2928d43a6210519961a7a27fc84b6eef2e59d74
Signed-off-by: William Wu <william.wu@rock-chips.com>
It adds the device tree bindings for PCIE/USB3 combo PHY
found on Rockchip SoCs.
Change-Id: Ia9c62cfc248b055fc2d7ced66b5b7620f7e220e2
Signed-off-by: William Wu <william.wu@rock-chips.com>
The power domains are supplied by regulators. Add support for them so
that the regulators are properly turned on before a domain is powered up
and turned off when a domain is powered down.
Change-Id: I43ad569e1b82a8e818cbbf2ffcfa6a965d993bbf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The scl rise time of I2C0 is 200ns, so it can use 400K frequency.
Change-Id: I80933698ff7576b9406213aa50becc7736951a8d
Signed-off-by: David Wu <david.wu@rock-chips.com>
In the TRX mode, if there was a nack signal at the hardware's
tx, we can get start and nack ipd from the I2C_IPD register,
which will enter nack process, send stop command, change the
state to stop, and enter the handler of stop irq, but the stop
irq may not be generated, it has a latency. So the log will like
this:
[ 69.961944] rk3x-i2c ff650000.i2c: unexpected irq in STOP: 0x10
[ 70.959690] rk3x-i2c ff650000.i2c: timeout, ipd: 0x00, state: 4
This error log will confuse us, it is not easier to locate the problem,
we should get nack error at this time, and processing stop interrupt at
the next, then complete this i2c job.
Change-Id: I073ef288557b1b6f525d936e8f32d9d165c81ec4
Signed-off-by: David Wu <david.wu@rock-chips.com>
The bit7 of I2C_IPD register also needs to be clean, otherwise,
it will always exist.
Change-Id: Iee01bffd83909e84ed99c9fab821e621c970efd3
Signed-off-by: David Wu <david.wu@rock-chips.com>
1.Change the format to MEDIA_BUS_FMT_UYVY8_2X8.
2.Add the PIXEL_RATE for control handlers.
Change-Id: I4f40e3d90765c12702210f88ad60f2147d328456
Signed-off-by: Leo Wen <leo.wen@rock-chips.com>
200ms is too long which will make cts/gts fail,100ms
is enough in fact.
Change-Id: Ifa0c58a9cf878936f6fbc9074cf26ce3d10a3ab4
Signed-off-by: Xinhuang Li <buluess.li@rock-chips.com>
200ms is too long which will make cts/gts fail,100ms
is enough in fact.
Change-Id: I88c75c66fcb7831afb7c8a74de2f1b3d754b84aa
Signed-off-by: Xinhuang Li <buluess.li@rock-chips.com>
