In some error case, it may fail to set the NAK bit
or Disable bit for endpoint when do ep deactivate
operation. We need to use wait-till-ready timeout
loop for ep deactivate instead of while loop.
Change-Id: I0e5ed61b2528f89910333c5eb907677e492fe3a0
Signed-off-by: William Wu <william.wu@rock-chips.com>
The frame num of isoc ep is initialized to 0xFFFFFFFF in
ep_enable and start_next_request(), and then in the NAK
interrupt handler, it will check if the ep frame num is
0xFFFFFFFF, then reset the frame num to 0 and start next
request.
But if we dequeue the isoc ep request if it's already
enqueued, if may fail to call complete_ep() -> start_
next_request(), so the isoc ep frame num can't be reinit
to 0xFFFFFFFF, this cause NAK interrupt handler check
the frame num incorrectly, and fail to start next request.
Change-Id: Iab8526f6e3979347bdbe6c49525ec0ba8130d4bc
Signed-off-by: William Wu <william.wu@rock-chips.com>
The dwc_otg_ep_start_zl_transfer() can be called from irq
handler in the top half, so don't print additional log to
avoid wasting too much time in interrupt handling.
If someone needs to dump verbose log, just set the debug
level to appropriate value.
Change-Id: If6fb8a22e0c42fb2b629c3a82d8e632254434784
Signed-off-by: William Wu <william.wu@rock-chips.com>
Sometimes we found the usb device could not connect to the HUBs when
the cable plug in and out constantly, the root cause is "USB RESET"
was missed from these HUBs, and we only try 2 times to reconnect.
This patch as one workaround to increase reconnect times to 6, and
add the delay time (3.5ms-4ms) after DCTL.SftDiscon bit was clear.
Change-Id: I57cfe5dc68e6d3d67c20771423dae29542ed047d
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
According to DWC2 databook V3.10a, 5.3.5.14 Device Threshold
Control Register (DTHRCTL), it recommends that the Transmit
Threshold Length (TxThrLen) is to be the same as the programmed
AHB Burst Length (GAHBCFG.HBstLen), on Rockchip platform the
value is 16.
Change-Id: I6427e3a3fc7b57e85229cdf4b9c5fff878b919b6
Signed-off-by: William Wu <william.wu@rock-chips.com>
Move last_id property from static to struct dwc_otg_device as a static
global variable to support PM suspend process.
Change-Id: I7729095339aed3dcca6481005f249c855ebbdb3c
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
According to 'DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG)
Programmer's Guide' 2.1.3.3 Dedicated FIFO Mode with Thresholding,
We can use threshold to support the following case:
1. To have a smaller FIFO size;
2. To have faster DMA response;
The threshold is useful for rockchip platforms which has a smaller
FIFO size and try to support three isochronous back-to-back packets
(high bandwidth).
And we also need to set GAHBCFG.HBstLen to INCR16 for high bandwidth
endpoints. If you want to support high bandwidth endpoints, it needs
to add a new property 'rockchip,high-bandwidth' in dts usb node.
Change-Id: I0c1d373cdaa51f22c15484912b752fb0b6ad4b9c
Signed-off-by: William Wu <wulf@rock-chips.com>
The SPDIF receiver is a self-clocking, serial, unidirectional
interface for the interconnection of digital audio equipment
for consumer and professional applications.
Change-Id: Ic73337671b37c8c45352e523a875281edd552d1b
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Reorder mipi configuration sequence for rk3288/rk3399
according to ip reference
Add comments to explain the sequence and running state
All mipi phy1 are controlled by isp
Change-Id: Ib5ad9edac4229acb5fa7f2088a9601d210a816f4
Signed-off-by: Allon Huang <allon.huang@rock-chips.com>
In order to cover the chips passed cp test program(1.3g 1.175v).
Change-Id: I4e19aefd914258e8d1e6d331b6f584aa7d0c4822
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
https://android.googlesource.com/kernel/configs
7a4e85661078 ("Enable options required by netd.")
The netd in master requires some additional options to be enabled for
the new (non-optional) XfrmController functionality.
Change-Id: I12677ee23774c2cdf899b04d5da204ff1ffc74de
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
dw-mmc got its reset-properties specified, so add the softresets
for it on the rk3399.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
(Cherry-picked from 04dc7f6203)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Conflicts:
arch/arm64/boot/dts/rockchip/rk3399.dtsi
Change-Id: I69b8cfeef113a259b930308965e33b915026a3d7
The aclk_vop is limited by vio_limit_freq and RK3288_LIMIT_PLL_VIO1
set as 410MHZ. if bind dsi to vopl (the clk freq will be 272MHZ),
it will be some scenarios with insufficient frame rates
Change-Id: I2fe15d51c579dbc5fe666cfb320055f0e179d2fc
Signed-off-by: Chen Jinsen <kevin.chen@rock-chips.com>
Fix vcodec_remove errors:
1. vcodec_remove needs to call corresponding subdev remove according to
subdev count.
2. Kernel vpu_session has to be freed with main device rather than
subdev remove.
3. Workqueue should be clear on device remove.
4. devfreq_unregister_opp_notifier and dev_pm_opp_of_remove_table
should be call to insure next insmod's success.
5. These is a great defect on subdev probe: the subdev has no
corresponding driver. The connection on main device and subdev is only
the dts name. This should be fixed in next framework. And now we have
to clear the resource allocated in subdev then we can insure next
insmod's success.
Change-Id: I336331e9e88564a5602796755f02af1786ddd7f9
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
These clocks do not assign default clock frequency, and use the
default cru register value to get frequency, so if cpll increase
frequency, these clocks also increase their frequency, that may
exceed their signed off frequency. So assign default clock for
them to avoid it.
NOTE: on none of the boards currently in mainline do we expect
CPLL to be anything other than 800 MHz, but some future boards
might have it. It's still good to be explicit about the clock
rates to make diffing against future boards easier and also to
rely less on BIOS muxing.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit e702e13f0b)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: If6a2341e2797f3c35f90fe1c621b1df13632694e
The ACLK_VIO is a parent clock used by a several children,
its suggested clock rate is 400MHz. Right now it gets 400MHz
because it sources from CPLL(800M) and divides by 2 after reset.
It's good not to rely on default values like this, so let's
explicitly set it.
NOTE: it's expected that at least one board may override cru node and
set the CPLL to 1.6 GHz. On that board it will be very important to be
explicit about aclk-vio being 400 MHz.
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 3f7f3b0fb4)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Conflicts:
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
Change-Id: Iadd22356e399e8d9b3a1f2bec981f2b41d813f3c
Per testing, this can reduce the memory latency and d8 gets
better scores.
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit bb4b6201d2)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I6f305e0bc60a91f18f606fb7a8012d80fcd378b5
In drivers/mmc/core/host.c, there is "max-freqeuncy" property.
It should be same behavior, So Use the "max-frequency" instead of
"clock-freq-min-max".
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit c49590691f)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Conflicts:
arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
Change-Id: I92f321b167cf4af9bb91e4814e797f0429ad80af
CVE-2017-0630
This likely breaks tracing tools like trace-cmd. It logs in the same
format but now addresses are all 0x0.
Bug: 34277115
Change-Id: Ifb0d4d2a184bf0d95726de05b1acee0287a375d9
Signed-off-by: Jian Qiu <qiujian@rock-chips.com>
CVE-2016-6684
An information disclosure vulnerability in Sync could enable a local
malicious application to access data outside of its permission levels.
The format specifier %p can leak kernel addresses while not valuing
the kptr_restrict system settings.
The fix is designed to use %pK instead of %p, which also evaluates
whether kptr_restrict is set.
Change-Id: I6d52a4d6193770b3fa1479a1086a5d73a210de07
Signed-off-by: Jian Qiu <qiujian@rock-chips.com>
The frame_overrun flag is used to indicates
SOF number (current_frame) overrun in DSTS
and the target_frame over DSTS_SOFFN_LIMIT.
Clear the frame_overrun flag only if target_frame
below DSTS_SOFFN_LIMIT and current_frame less
than target_frame.
Change-Id: I91cf9001324a9bbbcc4bc28b335695d607fb69d4
Signed-off-by: William Wu <william.wu@rock-chips.com>
The default period size is only 64 frames, this
will cause usb audio playback with noise via
internal audio codec. This patch sets the period
size to (snd->rate / 10), and also sets the buffer
size to snd->rate.
Change-Id: I4a4eb1b4dd79aec65f5c44eacd8a2fa101dfbd1b
Signed-off-by: William Wu <william.wu@rock-chips.com>
The f_audio_disable() doesn't disable usb ep, and
this cause usb enumeration fail. So add usb ep
disable operation.
This patch also reinitializes the opts->bound flag
to false in f_audio_free(), and then it can setup
ALSA audio device again in f_audio_bind().
Change-Id: I7b10630f5085b1a03792bc4b9e7eabb02d2bd5a2
Signed-off-by: William Wu <william.wu@rock-chips.com>
Adds pm_runtime support for dwc2, so that power domain is
enabled only when there is a transaction going on to help
save power.
Change-Id: I318552774d20eeaed521ff179f99b2551ee24183
Signed-off-by: William Wu <william.wu@rock-chips.com>
