Make hwc work correct when handle a 8K input source
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I77ee3c13f5c884fbdd9eec72b02998e10bbc3425
IMX415 is supposed to be the default sensor on rk3588 evb boards.
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Change-Id: I4b2ea0f57c2510d46ea5c0b3416d536a2e7bc898
Just as the commit 25e44a6ed98b("bq25700: register otg vbus regulator")
said that there will be some problems with the current vbus control,
and the patch has registered the otg vbus regulator in the charger ic
driver, then the otg vbus regulator can be referenced in the fusb302 node.
Change-Id: Id4c9f866a3d131eee6f732300ff642a7f5489672
Signed-off-by: Wang Jie <dave.wang@rock-chips.com>
Set SSC Modulation rate to 31.2 KHz that can pass the compliance test
and have a better margin.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: Iaf82e4803a9ccb196d21d9a02a93293be0dd053e
- Only check link retrain in short hpd pulse
- Always do link train in modeset
- Fix link retrain condition
- Add sink count check
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ifed1d706dcda5ac79322271ec59c2f1a5a79262b
For Type-C PD driver using the tcpm framework and charger ic
(bq25700) output otg vbus solution. Because the dwc3 driver
cannot know whether the Type-C PD device sends DR_swap and
PR_swap messages, there are some problems with the charger ic
vbus control:
(1) rk3588s as sink, Type-C device sends DR_swap Message, u2phy driver
will send enable otg vbus notification to charger ic driver;
(2) After the Type-C device sends PR_swap Message to realize the
Sink->Source or Source->Sink switch, the charge ic driver cannot
dynamically enable or disable the otg vbus;
Based on the above problems, an otg vbus regulator is registered in
the charge ic driver for use by the fusb302 (Type-C PD controller chip)
driver, the otg vbus control is transferred to the tcpm framework.
In some cases (for example, the hardware does not have a PD chip),
in order to be compatible with switching from a lower version kernel
(kenrel-4.4/4.19) to a higher version kernel(kernel-5.10), dts will not
be modified. the software registration of the otg vbus regulator fails,
the vbus extcon mechanism will be registered.
Signed-off-by: Wang Jie <dave.wang@rock-chips.com>
Change-Id: I721abcb214795c0024e200b10ec3ab1d4a9b790a
Fixes: 7534ec9a51 ("arm64: dts: rockchip: rk806: bind the rk806 to the rk3588")
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I01cd29ea965fc3a03e68a02f1a6a18ad5c44a73c
slove following issues:
- socket buffer is over;
- store phyaddr;
- get max delayline value for rk3588;
- split mac setting and phy setting for loopback to fix flow;
- add rgmii-rxid interface loopback;
- enable mtl configuration for multi queue;
- use phy softreset instead of hard reset.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I8da5a42948b34bf4a256a6f425c0ed98590ddea6
Parse and set assigned clocks configuration at the child node level.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I745090ebc2a3531c51557600fdb69867d7216684
According to the application scenario, DP0/DP1 may be bind to the
same vp port, or different vp port. The corresponding bit in output_if
needs to be set or cleared correctly.
Change-Id: I880946d0c61a209d5a16ff7d2aada43f87a075c5
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Because the usb3_0 super-speed phy driver is ready, let's
remove the maximum-speed limit for usb3_0 on nvr demo board.
Add also enable the usbdp_phy1_u3 to force usb3_1 to u2 only.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: If8835a667ad9e561d0291130b8fd1fbbe0fc6206
We should check PMU_BISR_STATUS register for
pd on/off status when bisr memory repair is
enabled.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: If1d0927551ddea9757c70b3a948367132a83ed5c
It's too late to set the aux channel polarity. Some
sink device will not send attention cmd to indicate
hpd plug event. Setting the aux channel polarity earlier.
When detecting the connected status is disconnected,
Setting the gpio status to low.
Fixes: 8081c70a82: ("phy: rockchip: usbdp-phy: add pointer check, avoid NULL pointer")
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Ie653a043f9d3cecf489846d7edbd6eca73f5ee28
PCIe need pipe clock for interface with phy;
Note that pcie controller also need its clock(has been set critical)
ACLK_PHP_GIC_ITS, and ACLK_PCIE_BRIDGE(has been set as parent).
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I98b2c001e8d0568af482cef8702a73a6cbd661f6
enable ROCKCHIP_HDMI ASoC driver to report jack status.
Signed-off-by: XiaoTan Luo <lxt@rock-chips.com>
Change-Id: I61dd19266747cfa2eb97030c107d95924f80f03d
Compared to 4.19, there are many new algorithm boundary
condition tests in 5.10. Drivers need to be fixed to
pass these tests and increase driver robustness.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: I597a478a5cfff5fa6c5389f45adec21acb63c68e
Reads the extended DPRX caps (%DP_DP13_DPCD_REV) if present.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I5c442e4c92917e136665b3dd5554abef9b7c81e5
