According to commit b350bee5e, use SYNC_SKCIPHER_REQUEST_ON_STACK
Change-Id: I2f81640b39e2f9b9d38534dfe633196158dff89b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
1.Support after SFC ver 4
2.If the io rate is high than 100MHz, enable SFC delay line in
default
3.Get id byte as data pattern
Change-Id: Ia405771c0bc94eddaa45e1d85c7fa10a85c40531
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
From test, sram_init_done can be used as a indicator to
see if phy power and input clock work find. Let's yell out
error is anything wrong with phy.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I5493e32ec5a9a6a8f6fc45e95618a657d9a21a67
We finally decide to set 16 for tx delay in driver, so no need for
dts to set it now.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I642ed3039db5410ca478b255166d07a035e971aa
According to the new test result, set tx delay to 16
by default.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I8e0bacfbf14f8c5db60a4d56a624d63c49e23051
This change amends the below features.
- Checked the mailbox channel status before send message.
- Used the con_priv variable to handle the channel private data.
- Added the spinlock cfg_lock to protect the register R/W.
- Added shared channel irq support.
- Optimized the interrupt handler can receive B2A message proactively.
Change-Id: If1939e51e821307788ab59dd4ef874a20a6568e2
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Fix up the rx\tx err cnt.
Support Auto Retransmission Mode.
Support rx frame clean.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Ib5a226c975cb6cb4229f8a30995ce09740de749e
Before the change: The sizeof rk3568_pll_rates = 2544
Use union: The sizeof rk3568_pll_rates = 1696
In future Soc, more PLL types will be added, and the
rockchip_pll_rate_table will add more members,
and the space savings will be even more pronounced
by using union.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Link: https://lore.kernel.org/r/20210511090726.15146-1-zhangqing@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 23029150a0
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git v5.14-clk/next)
Change-Id: Ia8f038861c327feb41602cc9a997e82333fae67b
There is a deadlock when the reply of FUSE_CANONICAL_PATH from user-
space client, because the kern_path function will issue a new request
and wait the respond from client which has been in wait state. The ba-
cktrace is like this:
<6>[ 518.977731] ntfs-3g S 0 2138 1 0x04000000
<4>[ 518.977745] Call trace:
<4>[ 518.977757] __switch_to+0x130/0x13c
<4>[ 518.977767] __schedule+0x740/0x964
<4>[ 518.977777] schedule+0x70/0x90
<4>[ 518.977794] __fuse_request_send+0x1a0/0x340
<4>[ 518.977808] fuse_simple_request+0x178/0x1c8
<4>[ 518.977818] fuse_lookup_name+0xfc/0x220
<4>[ 518.977829] fuse_lookup+0x48/0x134
<4>[ 518.977842] __lookup_slow+0xc8/0x154
<4>[ 518.977853] walk_component+0x1c0/0x728
<4>[ 518.977863] path_lookupat+0xa8/0x208
<4>[ 518.977875] filename_lookup+0x8c/0x190
<4>[ 518.977887] kern_path+0x30/0x3c
<4>[ 518.977901] fuse_dev_do_write+0x79c/0x114c
<4>[ 518.977914] fuse_dev_write+0x60/0x84
<4>[ 518.977928] do_iter_readv_writev+0x11c/0x158
<4>[ 518.977941] do_iter_write+0x7c/0x1b8
<4>[ 518.977953] vfs_writev+0x84/0xe8
<4>[ 518.977966] do_writev+0x78/0x114
<4>[ 518.977979] __arm64_sys_writev+0x1c/0x24
<4>[ 518.977992] el0_svc_common+0x98/0x160
<4>[ 518.978005] el0_svc_handler+0x5c/0x64
<4>[ 518.978015] el0_svc+0x8/0xc
Fixes: fa199896a3 ("ANDROID: fuse: Add support for d_canonical_path")
Signed-off-by: Cliff Chen <cliff.chen@rock-chips.com>
Change-Id: I13487e5c956c4537c2554a44208d6664653ef4f1
By default fsync option, if fsync is called frequently, and suddenly
lost power, the POR will consume too much memory at mounting, this
process may be very slow due to a large number of swapping.
Change-Id: I8235098cca062d7ab58af4ebed414aed9aba6c75
Signed-off-by: Cliff Chen <cliff.chen@rock-chips.com>
Signed-off-by: Alex Wang <alex.wang@rock-chips.com>
The f_blocks of statfs include file system overhead，it is not normal
usage of Posix.
Change-Id: If481626b08c05290626938586e2dc721690f1a91
Signed-off-by: Cliff Chen <cliff.chen@rock-chips.com>
The reserved root blocks is not enough for booting Android due to
the limit of 0.2% if the fs size too small. so we add a new mini-
mum limit is 128MB.
Change-Id: I5af3b182001d27e4d18b4090c5270bbb2ac6253b
Signed-off-by: Cliff Chen <cliff.chen@rock-chips.com>
This DWC2 driver has handled the unaligned DMA address problem
for urb->transfer_buffer and split in transfer. But it still
has problem to handle the isoc out transfer with unaligned DMA
address.
I test an USB Audio device which supports 24bits 96KHz 3LE format:
usb 1-1: new full-speed USB device number 2 using dwc2
usb 1-1: New USB device found, idVendor=21b4, idProduct=0083, bcdDevice= 1.06
usb 1-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
usb 1-1: Product: AudioQuest DragonFly Black v1.5
usb 1-1: Manufacturer: AudioQuest
usb 1-1: SerialNumber: AQDFBL0100023815
When play 24bits 96KHz WAV file, noise occurs.
The rootcause is that the DWC2 controller use internal DMA to
transfer USB audio data, and the DMA address of data buffer must
be 4 bytes aligned, otherwise, the dwc2 will fail to transfer the
data. In this test case, the USB audio may transfer 572 bytes or
582 bytes in one usb transaction. And one URB contains multiple
usb transactions, if the DWC2 transfer the 582 Bytes in the middle
of the URB, the DMA address will not be 4 bytes aligned.
This patch allocates new aligned buf for isoc out transfer with
unaligned DMA address.
For isoc split out transfer, this patch sets the start schedule at
the 2 * DWC2_SLICES_PER_UFRAME to transfer the SSPLIT-begin OUT
transaction like EHCI controller. Without this patch, the SSPLIT-begin
OUT transaction starts in the seventh microframe, and this makes the
USB HUB unhappy. This patch sets the the SSPLIT-begin OUT transaction
starts in the first microframe.
Change-Id: I251ccf804e062312f9bd348552493f3bab504beb
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Channel halt with unknown reason happens in the following case:
DWC2 + USB 2.0 HUB + HS Device + FS Device
The HS Device is an optical fingerprint:
usb 1-1.4: USB disconnect, device number 5
usb 1-1.4: new high-speed USB device number 6 using dwc2
usb 1-1.4: New USB device found, idVendor=28ed, idProduct=7000
usb 1-1.4: New USB device strings: Mfr=1, Product=2, SerialNumber=3
usb 1-1.4: Product: Aratek Capture Device
usb 1-1.4: Manufacturer: Aratek
The FS Device is an ID card identification module:
usb 1-1.3: new full-speed USB device number 9 using dwc2
usb 1-1.3: New USB device found, idVendor=0400, idProduct=c35a
usb 1-1.3: New USB device strings: Mfr=0, Product=0, SerialNumber=0
When the issuse occurs, it always dump the error log:
dwc2 ff540000.usb: dwc2_hc_chhltd_intr_dma: Channel 13 - ChHltd set, but reason is unknown
dwc2 ff540000.usb: hcint 0x00000002, intsts 0x04000021
dwc2 ff540000.usb: dwc2_update_urb_state_abn(): trimming xfer length
Change-Id: I93ef92007a3d1a91485c764565c8f532ce1ac1aa
------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at drivers/usb/dwc2/hcd.c:2796 dwc2_assign_and_init_hc+0x554/0x8e4()
Modules linked in: bcmdhd
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.4.143 #3
Hardware name: Generic DT based system
[<c010f854>] (unwind_backtrace) from [<c010bb84>] (show_stack+0x10/0x14)
[<c010bb84>] (show_stack) from [<c03ed8b4>] (dump_stack+0x7c/0x9c)
[<c03ed8b4>] (dump_stack) from [<c012737c>] (warn_slowpath_common+0x88/0xb4)
[<c012737c>] (warn_slowpath_common) from [<c0127488>] (warn_slowpath_null+0x18/0x20)
[<c0127488>] (warn_slowpath_null) from [<c05c8314>] (dwc2_assign_and_init_hc+0x554/0x8e4)
[<c05c8314>] (dwc2_assign_and_init_hc) from [<c05c8788>] (dwc2_hcd_select_transactions+0xe4/0x178)
[<c05c8788>] (dwc2_hcd_select_transactions) from [<c05ca0e4>] (dwc2_release_channel+0x1b8/0x1cc)
[<c05ca0e4>] (dwc2_release_channel) from [<c05cbaa8>] (dwc2_hc_n_intr+0x4a0/0x728)
[<c05cbaa8>] (dwc2_hc_n_intr) from [<c05cc1dc>] (dwc2_handle_hcd_intr+0x4ac/0x4d8)
[<c05cc1dc>] (dwc2_handle_hcd_intr) from [<c05b247c>] (usb_hcd_irq+0x24/0x38)
[<c05b247c>] (usb_hcd_irq) from [<c017dea4>] (handle_irq_event_percpu+0xa8/0x28c)
[<c017dea4>] (handle_irq_event_percpu) from [<c017e0c0>] (handle_irq_event+0x38/0x5c)
[<c017e0c0>] (handle_irq_event) from [<c0181560>] (handle_fasteoi_irq+0xa8/0x124)
[<c0181560>] (handle_fasteoi_irq) from [<c017d5cc>] (generic_handle_irq+0x18/0x28)
[<c017d5cc>] (generic_handle_irq) from [<c017d890>] (__handle_domain_irq+0x88/0xb0)
[<c017d890>] (__handle_domain_irq) from [<c010142c>] (gic_handle_irq+0x44/0x74)
[<c010142c>] (gic_handle_irq) from [<c010c554>] (__irq_svc+0x54/0x90)
This patch only clears the unmask interrupts to avoid trigger
unknown Channel Halted interrupt. However, if the Channel Halted
interrupt happens unexpected, we need to check if the urb->length
is 4-byte alignment in dwc2_update_urb_state_abn(), this can help
to avoid the above warning.
Change-Id: I41f5ea7b6361502019311ed1527137374e93059d
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Refer to lowlevel mechanism of dwc2, amend the PHY operation
process in case of unbalance for power on and off as well.
This patch fix unbalanced phy power management if otg cable
plug in between the completion of dwc2 probe and udc_start.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: Ic0c2811ed84f8f46e99e03eff44c9d20a791e05f
The usb phys need to be controlled dynamically on some Rockchip SoCs.
So set the new HCD flag which prevents USB core from trying to manage
our phys.
Change-Id: I2d1197f42fe49bc4e454954481f344256fddb557
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The dwc2 programming guide section 3.5 'Halting a Channel'
says that the application can disable any channel by
programming the HCCHARn register with the HCCHARn.ChDis
and HCCHARn.ChEna bits set to 1'b1. This enables the
dwc_otg host to flush the posted requests (if any) and
generates a Channel Halted interrupt.
But it also requires that channel disable must not be
programmed for non-split periodic channels. At the end
of the next uframe/frame (in the worst case), the core
generates a channel halted and disables the channel
automatically.
If we disable non-spilt periodic channels to halt the
channels, it will easily to cause data transfer fail.
A typical case is take photo with usb camera or close
usb camera, Specifically, the observed order is:
1. uvc driver calls usb_kill_urb
2. usb_kill_urb calls urb_dequeue to cancel urb
3. urb_dequeue call dwc_otg_hc_halt to disable
non-spilt periodic channels
4. usb core doesn't halt the non-spilt periodic
channels immediately, and the application
reallocates the channels for other transactions
without waiting for the HCINTn.ChHltd interrupt.
5. uvc driver calls usb_set_interface to start
control transfer, and gets a channel which used
for non-spilt periodic transfer before. The core
generates a channel halted and disables the channel
automatically. This cause control transfer fail.
Change-Id: I95424a99b77b552396a9fb95a5058258270ed4c2
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The commit e6f2f6d63e ("usb: dwc2: power on/off phy for
otg mode") aimed to control phy power for otg mode, but
it also introduced a new problem, so we fix it.
This patch keep phy power on for otg if current mode is
host during dwc2 probe, otherwise the enumeration will
fail with the following error log:
Cannot enable. Maybe the USB cable is bad?
Cannot enable. Maybe the USB cable is bad?
attempt power cycle
Cannot enable. Maybe the USB cable is bad?
Cannot enable. Maybe the USB cable is bad?
unable to enumerate USB device
Change-Id: I17a4cab6f0337fdc0923989aea8613bfbe1a9e9b
Fixes: e6f2f6d63e ("usb: dwc2: power on/off phy for otg mode")
Signed-off-by: Feng Mingli <fml@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The frame_overrun flag is used to indicates
SOF number (current_frame) overrun in DSTS
and the target_frame over DSTS_SOFFN_LIMIT.
Clear the frame_overrun flag only if target_frame
below DSTS_SOFFN_LIMIT and current_frame less
than target_frame.
Change-Id: I91cf9001324a9bbbcc4bc28b335695d607fb69d4
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Adds pm_runtime support for dwc2, so that power domain is
enabled only when there is a transaction going on to help
save power.
Change-Id: I318552774d20eeaed521ff179f99b2551ee24183
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The operation mode of controller will change to peripheral when
resume if PD is power off during suspend, current code disconnect
hcd and set lx state to L3 in this case to make sure the controller
will be reinit in device mode, but that's not enough, the op_state
is still host which is change when init or ID change interrupt
occur. If the ID change happened after suspend the driver would
miss the interrupt, so when the application call the pullup function
to stop gadget and start again to change to another function, the
disconnect gadget operation can't be done and the gadget restart
directly. This will result in NULL point when gadget work. This
patch set op_state to OTG_STATE_B_PERIPHERAL when resume in this
case.
Change-Id: Ifbafb7fae43d634cfa879c9a066d1e114db4196e
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The controller will reset and run into error state if turn
off power when suspend in host mode. This patch stop hcd to
make the controller into L3 state to make sure that the
controller and driver state will reset when resume.
Change-Id: If66bc1a249e919f440ecde0c66f18dabde0b2e62
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The commit dc71e51944 ("usb: dwc2: make otg manage lowlevel
hw on its own") aimed to control the clk and phy power for
otg mode, but it also introduced lost of new problems, so we
revert it.
This patch only controls phy power for otg mode, it can fix
the dwc2 udc start fail issue with the following error log:
dwc2_hsotg_init_fifo: timeout flushing fifos (GRSTCTL=80000430)
dwc2_core_reset() HANG! Soft Reset GRSTCTL=80000001
bound driver configfs-gadget
dwc2_core_reset() HANG! Soft Reset GRSTCTL=80000001
Change-Id: Id6996aecab7f0aaaf12530b7a377144e23ef1667
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
When handle disconnect of the hcd during bus_suspend, hcd
needs to resume its root hub, otherwise the root hub will
not disconnect the existing devices under its port.
This issue always happens when connecting with usb devices
which support auto-suspend function (e.g. usb hub).
(am from https://patchwork.kernel.org/patch/9751469/)
Change-Id: I663fdea73f36e89130d9a250612363968cbff941
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Originally, dwc2 just handle one otg clock, however, it may have
two or more clock need to manage for some vendor SoCs, so this
reworks to use bulk clock APIs.
Change-Id: I661297ef908d9eace2215205018fa94d12cea128
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The DWC2 driver auto detects the hardware and enable
the gadget descriptor DMA if the DWC2 IP supports it.
However, the gadget descriptor DMA has some unexpected
compatibility issues, so we use buffer DMA instead of
desc DMA.
Change-Id: I1fed77f7d9bec1e0916b44d80813fb6248d461f0
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
LPM feature of DWC2 module integrated in Rockchip SoCs doesn't work
properly or needs some additional handling, so disable it for now.
Without disabling LPM feature, the USB ADB communication fail with
the following error log:
dwc2 ff580000.usb: new address 27
dwc2 ff580000.usb: Failed to exit L1 sleep state in 200us.
dwc2 ff580000.usb: dwc2_hsotg_send_reply: cannot queue req
dwc2 ff580000.usb: dwc2_hsotg_process_req_status: failed to send reply
dwc2 ff580000.usb: dwc2_hsotg_enqueue_setup: failed queue (-11)
dwc2 ff580000.usb: Failed to exit L1 sleep state in 200us.
Change-Id: I4e2b243fba2f1536c39f313232433cfd295113d6
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
usage:
(1) force host mode
echo 1 > /sys/devices/platform/ff770000.syscon/ff770000.syscon:usbphy/phy/phy-ff770000.syscon:usbphy.2/otg_mode
(2) force device mode
echo 2 > /sys/devices/platform/ff770000.syscon/ff770000.syscon:usbphy/phy/phy-ff770000.syscon:usbphy.2/otg_mode
Change-Id: I44fa1461076e6c0cd8aba1e2e444004cfb3f5271
Signed-off-by: Wang Jie <dave.wang@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
We found that the system was blocked in EHCI when perform suspend or
reboot on RK3288 platform, the root cause is that EHCI (auto) suspend
causes the corresponding usb-phy into suspend mode which would power
down the inner PLL blocks in usb-phy if the COMMONONN is set to 1'b1.
The PLL output clocks contained CLK480M, CLK12MOHCI, CLK48MOHCI, PHYCLOCK0
and so on, these clocks are not only supplied for EHCI and OHCI, but also
supplied for GPU and other external modules, so setting COMMONONN to 1'b0
to keep the inner PLL blocks in usb-phy always powered.
Change-Id: Ifb7f3d233cf72155aa54d20b15a62b683944a526
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
