When 4K x 2k 60Hz/50Hz tmds clock is above the max tmds clock, setting its
color to YUV420. A few TV edid declare that they can't support
4K x 2k 60Hz/50Hz YUV420, we still set color to YUV420 or 4K x 2k 60Hz/50Hz
tmds clock will over the limit.
Change-Id: Id57c9313ab52973927c578d0eb2a7b1b30cb9ec1
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
First, write hdcp key by "ProvisioningTool" if you want to
enable hdcp function, or else will auth fail.
To check whether the hdcp is enable or not
#cat /sys/class/misc/hdmi_hdcp1x/enable
0:hdcp is disabled
1:hdcp is enabled, hdmi screen will be pink if it is failed;
2:hdcp is enabled, hdmi screen will be normal if it is failed;
Enable or disable hdcp function
#echo 0 > /sys/class/misc/hdmi_hdcp1x/enable
#echo 1 > /sys/class/misc/hdmi_hdcp1x/enable
#echo 2 > /sys/class/misc/hdmi_hdcp1x/enable
Get the status of hdcp
#cat /sys/class/misc/hdmi_hdcp1x/status
The result will be one of the follow list:
hdcp disable;
hdcp_auth_start
hdcp_auth_success;
hdcp_auth_fail;
unknown status.
Change-Id: Iac6c7d6a1196ce9cf2869d7916bbe6c8941ec13b
Signed-off-by: Huicong Xu <xhc@rock-chips.com>
Hdmi suspend or resume may be called before hdmi initialization. We must
verify that hdmi is initialized first.
Change-Id: I2a680209e64b9c1aebc2d9ee19d543927137afd0
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
When system shutdown, shutdown interface will be called.
Hdmi should be disabled when system shutdown.
Change-Id: I09ec1d7d3801bf8a8277c91072fa09bd1b430809
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
This patch delete the mutex in dw_hdmi_suspend. For there is no
need to use mutex to protect disable_irq. And the same mutex is
also used in the dw_hdmi_irq, mutex deadlock will occur when
dw_hdmi_suspend and dw_hdmi_irq are called at the same time.
Change-Id: I8cb6a6483aa4d32882e814656dd93317b5da9ad3
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
If HDMI HPD detect delayed work won't be cancel, system will
crush because clk and PD has been disabled. So HDMI HPD detect
workqueue should be flushed when system suspend.
Change-Id: Idb8018c2efcffc3aee5fd80872f1270360809235
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
If edid can't be got when hdmi plug in, hdmi color depth mask and format
won't be updated. The color list in the setting are those of the previous
TV. This commit fix the error.
Change-Id: I5ed4be5efa2a69be0b58489f58a3af5de9912292
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
According to HDMI 1.4b specification: If the transmitted video
format has timing such that the phase of the first pixel of
every Video Data Period corresponds to pixel packing phase 0
(e.g. 10P0, 12P0, 16P0), the Source may set the Default_Phase
bit in the GCP. The Sink may use this bit to optimize its filtering
or handling of the PP field.
This means that for 10-bit mode the Htotal must be dividable by 4;
for 12-bit mode, the Htotal must be divisible by 2.
Change-Id: I02e632d095141cbabcba06dc1321ae0dc69dc736
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
When the color depth is 24 bits per pixel video, the CD
field in General Control Packet should be "Color Depth
not indicated", then the colordepth in register vp_pr_cd
& csc_scale should assign to zero.
BUG=chrome-os-partner:38212
TEST=speedy board, Test with Agilent Technologies U4002A
HDMI Protocal Analyzer
Change-Id: Ifd5767d339fdbff11e234ec0891c8f3df1dd66a5
Reviewed-on: https://chromium-review.googlesource.com/261850
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Yakir Yang <ykk@rock-chips.com>
Commit-Queue: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Formula3 and Formula2 for csc decimation will cause hdmi yuv422
display err.
Formula3:
The pixel color of left 0-14 columns and right 0-12 columns is
err.
Formula2:
The pixel color of left 0-2 columns is err.
Change-Id: I94fdd5fd962a24fde02dde1fe3ac10437ad117ad
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Under following processes, rxsense will be not match the real
signal status.
1. HDMI plug in, irq is triggered.
2. HDMI irq is mute in dw_hdmi_hardirq, bring up dw_hdmi_irq.
3. For HDMI connection is not stable, phy_stat read in
dw_hdmi_irq may be zero, then hdmi->rxsense will be false.
4. Connection fallback to stable, but dw_hdmi_irq had not
unmute the irq, irq is not triggered again, and hdmi->rxsense
keep false.
5. repo_hpd_event inform HDMI is pluggned in, dw_hdmi_bridge_enable
is called to enable HDMI. For rxsense is flase, bridge is not
powered up.
When repo_hpd_event is called, we think HDMI connection is stable,
updating rxsense is reliable.
Change-Id: Ie1f52f65b15e9a603dad9200529202053528a390
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
This patch is an attempt to limit HDMI 2.0 SCDC setup when :
- the SoC embeds an HDMI 1.4 only controller
- the EDID supports SCDC but not scrambling
- the EDID supports SCDC scrambling but not for low TMDS bit rates,
while only supporting low TMDS bit rates
This to avoid communicating with the SCDC DDC slave uncessary, and
setting the DW-HDMI TMDS Scrambler setup when not supported by the
underlying hardware.
Change-Id: I8ec1b7c33f49e4a63196335589d11396c8b9fe0e
Reported-by: Rob Herring <robh@kernel.org>
Fixes: 264fce6cc2 ("drm/bridge: dw-hdmi: Add SCDC and TMDS Scrambling support")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Rob Herring <robh@kernel.org>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190315095414.28520-1-narmstrong@baylibre.com
(cherry picked from commit 836f90f9e2)
Introduce status node in debugfs to show HDMI output status,
such as phy status, color and eotf.
Here is a sample log:
PHY enabled Mode: HDMI
Pixel Clk: 594000000Hz TMDS Clk: 594000000Hz
Color Format: YUV422 Color Depth: 10 bit
Colorimetry: ITU.BT2020 EOTF: ST2084
x0: 0 y0: 0
x1: 0 y1: 0
x2: 0 y2: 0
white x: 0 white y: 0
max lum: 0 min lum: 0
max cll: 0 max fall: 0
Change-Id: I5d458b633dd3bd9aab67cc91f1695621937e58f5
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Application need to listen HDMI connector state when connector is
forced on/off, so we add switch_set_stat in dw_hdmi_connector_force.
Change-Id: I2b76a0a647eb6a4cfde7584e085f53540d0fa27f
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
After switching color, hdmi output signal may be unstable.
If AVMUTE is cleared too early, tv will display err.
Change-Id: I595180bfe6e014de5231bcd75ee259d5702121e0
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
There is no need to judge hpd status in atomic_begin and atomic_flush.
And this judgment may cause display error if TV make hpd status change
frequently.
Change-Id: I2ed87ef42b78a8faadc4bcc5b6b16d9390644903
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
This patch is only applicable to 3d frame packing
of progressive mode.
According to HDMI Specification 1.4b 8.2.3.2,
vertical toatal line is x2 of 2D vertical toatal line
and pixel clock frequency is x2 of 2D pixel clock frequency.
vdisplay += vtotal
mpixelclock *= 2
Change-Id: I097c25cd1a930635e33f0a7bc86797ad1c7ed607
Signed-off-by: algea.cao <algea.cao@rock-chips.com>
msgs[0].addr will be 0x30 when read edid with more than 2 block.
but still a read edid operation with write DDC_ADDR to
HDMI_I2CM_SLAVE register.So fix it.
Change-Id: I5f0cd9172acd4a68d5b54eaf99f17b45385a4263
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
To set dw hdmi i2c bus adapter scl clock rate, we introduce two device
tree parameter, ddc-i2c-scl-high-time-ns and ddc-i2c-scl-low-time-ns.
ddc-i2c-scl-high-time-ns: how many ns SCL hold high
ddc-i2c-scl-low-time-ns: how many ns SCL hold low
After measurement, 50KHz scl clock rate recommended configuration is:
&hdmi {
ddc-i2c-scl-high-time-ns = <9625>;
ddc-i2c-scl-low-time-ns = <10000>;
};
100KHz recommended configuration is:
&hdmi {
ddc-i2c-scl-high-time-ns = <4708>;
ddc-i2c-scl-low-time-ns = <4916>;
};
If dts parameter is not available, the default scl rate is 100KHz.
Change-Id: I6f6b0bf1694ab59e70da789ead99e15a53c93e4d
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
This patch add hdmi_output_colorimetry to support modify
hdmi output colorimetry. It could be following value:
- None
- IUT_2020
Default value is None, which means normal hdmi output
colorimetry.
Change-Id: Ib4883fd0553d9d4193c7295812d2c1433724fe63
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
CEA 861.3 spec adds colorimetry data block for HDMI.
Parsing the block to get the colorimetry data from
panel.
v2: Rebase
v3: No Change
v4: Addressed Shashank's review comments. Updated
colorimetry field to 16 bit as DCI-P3 got added
in CEA 861-G spec, as pointed out by Shashank.
v5: Fixed checkpatch warnings with --strict option.
Change-Id: Ia82d4c04edff53bd4d6c4411dd90391497140e85
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
(am from https://patchwork.kernel.org/patch/10861325/)
there are maximum TMDS clock limit, when the clock is out of range
reducing frequency by set color format to yuv420 and/or set color
depth to 8bit
Change-Id: I8b79de97329561bf0399d05c0264a5c818f844fc
Signed-off-by: xuhuicong <xhc@rock-chips.com>
If color depth is automatic, it is same as 8bit.
If tmdsclk > max_tmds_clock, fall back to 8bit.
Change-Id: Ia8cbf5206831ef99456ae59add94c6f8b5a33380
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
For some display device, max_tmds_clock is 0, we think
max_tmds_clock is 340MHz. If tmdsclock > max_tmds_clock,
depth should fall back to 8bit. And If display mode support
YCBCR420, output format is YCBCR420.
Because max tmds clk of RK3368 is 340MHz, hdmi output policy
is same as mentioned above.
It is need to check tmds clock rate at the last. So we move
depth checking into dw_hdmi_rockchip_select_output.
Change-Id: I27e029fc0171b175ddbfa453ed12854ab6a7432b
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
VOP irq is share with VOP mmu, so the irq_desc is point to the same
address, this maybe case the following bug:
vop_bind()
devm_request_irq() -> irq_desc->depth is 0
disable_irq() -> irq_desc->depth is 1
encoder/connector/panel maybe bind failed, so next step is:
vop_unbind()
……
vop_bind() again
devm_request_irq() -> because the irq_desc is share with VOP MMU,
the irq_desc isn't freed.so the depth is 1
disable_irq() -> irq_desc->depth is 2
next step when we want to enable_irq, the irq_desc->depth is 2, the GIC
will not enable VOP irq realy.
so we update the VOP irq control, delete the GIC VOP interrupt control.
after this the VOP interrupt only control by VOP interrupt register.
maybe we can enable_irq at vop_unbind when vop_bind failed to keep irq
balance, but the enable_irq() at vop_unbind() seem not friendly.
Change-Id: I30ee0b6973e8eebb9209b10d8bbbfb6cbcfb30e8
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
The Innosilicon Video Combo PHY not only supports MIPI DSI,
but also LVDS and TTL functions with small die size and low
pin count. Customers can choose according to their own applications.
Change-Id: I0e4a5f69af5cc967b5df0fb17a51c43cef9ea33f
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This patch adds more generic PHY modes to the phy_mode enum, to
allow configuring generic PHYs to the MIPI/LVDS/TTL mode by
using the set_mode callback.
Change-Id: Ib6966828011aa52f1f133449f69df46c2001a57b
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
PX30 vopb have win0, win1 and win2 layers.the formats they support below:
Win0: XR24 AR24 XB24 AB24 RG24 BG24 RG16 BG16 NV12 NV16 NV24 NA12 NA16 NA24
Win1/2: XR24 AR24 XB24 AB24 RG24 BG24 RG16 BG16
Only the win0 layer support NV12 format(video decode format).
So change to use win0 for video overlay layer and win1 for ui layer.
Change-Id: I7ef8bda4be908188700ca4d3f1df23a6336e02b2
Signed-off-by: Leo Wen <leo.wen@rock-chips.com>
AFAWK, there are four layers in RK3399's VOPB, and two layers for
RK3399's VOPL.
And RK3399's VOBL has the win0 and win2 layers, the formats they support
as below.
win0:
XR24 AR24 XB24 AB24 RG24 BG24 RG16 BG16 NV12 NV16 NV24 NA12 NA16 NA24
win2:
XR24 AR24 XB24 AB24 RG24 BG24 RG16 BG16
So only win0 layer supports NV12 format (for video decode format),
adjust the overlay for video and primary layer for display.
It didn't care this case if some platforms had handled the display in
application (e.g android), then on the Linux platform, it's hard to handle
the all kinds of cases in Display application, perhaps the linux needn't
this patch fixes it in the future.
Depend-CL:76144
Fixes: d82f1d3e58
("arm64: dts: rockchip: reasonable alllcation of VOP on rk3399 linux")
Change-Id: Id93b315b6e3ae670bf5ea4dc0a64e140c6e37e80
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
The zpos currently configure is the order in vop_win_data array,
which is related to the actual hardware plane.
But in the Linux platform, such as video hardware and camera preview,
it can only be played on the nv12 plane.
So set the order of zpos to PRIMARY < OVERLAY (if have) < CURSOR (if have).
Change-Id: Ia9ab3cb9225fd2c385703109afbfbb42a1564110
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
