Currently the driver does not implement suspend and resume PM ops.
However when system is entering suspend, the driver should prevent
submitting further runs to the hardware and wait for current run to be
finished. To resume playback after leaving sleep state, next run, if
available, must be submitted to the hardware.
This patch adds proper suspend and resume callbacks to handle this.
BUG=chrome-os-partner:38565
TEST=suspend and resume veyron_jerry several times with video playing
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/263662
Reviewed-by: Pawel Osciak <posciak@chromium.org>
Change-Id: Id07b7d681ef78655879ce77c9705b1c25231df9d
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Even though H264 standard allows arbitrary order of DPB entries, the
hardware requires picture with given POC to use the same DPB entry for
its whole lifetime. This means that the driver needs to reorder DPB
array to suit this requirement.
This patch modifies the driver to reorder H264 DPB and should fix
corruption issues when DPB array received from userspace does not meet
hardware requirements.
BUG=chrome-os-partner:38416
TEST=http://www.youtube.com/embed/YE7VzlLtp-4
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/263370
Reviewed-by: Pawel Osciak <posciak@chromium.org>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: Ibbd0e2bc4e527aadd21ef08ec68866678bf8a659
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Current code always assumed the maximum supported resolution to be
1920x1088, and minimum 8x4 however the real limits are 48x48 and 3840x2160
for decoder and 96x96 and 1920x1088 for encoder. This patch modifies the
driver to use correct limits and also fixes incorrect log message.
BUG=chrome-os-partner:38232,chromium:464920
TEST=Screen sharing of a window bigger than 1920x1088 to Jerry
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/261851
Reviewed-by: Pawel Osciak <posciak@chromium.org>
Change-Id: I0c51e5a9ad235716ee447e052455b97ed0c295de
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
If segmentation_enable flag is zero, no matter what
segmentation_update_flag is, we cannot set it to HW.
Before this patch, incorrect segmentation_update_flag
might be set to HW which caused hangout corruption.
BUG=chrome-os-partner:35531
TEST=make a video chat by hangout with other device.
Signed-off-by: ZhiChao Yu <zhichao.yu@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/242732
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
Tested-by: Tomasz Figa <tfiga@chromium.org>
Commit-Queue: Tomasz Figa <tfiga@chromium.org>
Change-Id: I86c00c27d3c97854db8c4164289fa434b29819ff
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
According to RK3288 TRM, the maximum worst case operating frequency of
VPU is 400 MHz, but by default it is set to 200 MHz. To fix (or work
around) performance issues with VP8 encoder, this patch bumps the
frequency to maximum possible value.
BUG=chrome-os-partner:35405
TEST=./video_encode_accelerator_unittest
--test_stream_data=tulip2-1280x720-1b95123232922fe0067869c74e19cd09.yuv:1280:720:11:out1280x720.ivf:1200000
--v
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/240644
Reviewed-by: Pawel Osciak <posciak@chromium.org>
Change-Id: I397139fe1195b74b8ebd516eae0968bccff7ef4b
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
This patch adds implementation of basic V4L2 APIs for decoder part of
the driver. It is still missing the hardware specific part, including
the hardware specific controls containing certain data precalculated
in userspace.
BUG=chrome-os-partner:33728
TEST=compile
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/237617
Reviewed-by: Pawel Osciak <posciak@chromium.org>
Change-Id: I3cad74aad3c6c4ac5e6b2123b5d93e3173b74c7a
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
DMA allocations might be subject to certain reqiurements specific to the
hardware using the buffers, such as availability of kernel mapping (for
contents fix-ups in the driver). The only entity that knows them is the
driver, so it must share this knowledge with vb2-dc.
This patch extends the alloc_ctx initialization interface to let the
driver specify DMA attrs, which are then stored inside the allocation
context and will be used for all allocations with that context.
As a side effect, all dma_*_coherent() calls are turned into
dma_*_attrs() calls, because the attributes need to be carried over
through all DMA operations.
BUG=chrome-os-partner:38873
TEST=compile
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/265363
Reviewed-by: Pawel Osciak <posciak@chromium.org>
Change-Id: I0e6c040cf820c194b6ca6f3e6355217496bd1532
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
When queuing buffers allow for passing the configuration store ID that
should be associated with this buffer. Use the 'reserved2' field for this.
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
BUG=chrome-os-partner:33728
TEST=build
Signed-off-by: Pawel Osciak <posciak@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/232583
Trybot-Ready: Tomasz Figa <tfiga@chromium.org>
Tested-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Wu-cheng Li <wuchengli@chromium.org>
Commit-Queue: Tomasz Figa <tfiga@chromium.org>
Conflicts:
drivers/media/v4l2-core/videobuf2-core.c
[rebase44(groeck): fixed conflicts; structural changes to match v4.4]
Signed-off-by: Guenter Roeck <groeck@chromium.org>
Conflicts:
drivers/media/v4l2-core/v4l2-compat-ioctl32.c
Change-Id: Ibb823e9369bec79645e09651b0dda006ed53ecc5
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
The ctrl_class is fairly pointless when used with drivers that use the control
framework: you can just fill in 0 and it will just work fine. There are still
some old unconverted drivers that do not support 0 and instead want the control
class there. The idea being that all controls in the list all belong to that
class. This was done to simplify drivers in the absence of the control framework.
When using the control framework the framework itself is smart enough to allow
controls of any class to be included in the control list.
Since configuration store IDs are in the range 1..255 (or so, in any case a relatively
small non-zero positive integer) it makes sense to effectively rename ctrl_class
to config_store. Set it to 0 and you get the normal behavior (you change the current
control value), set it to a configuration store ID and you get/set the control for
that store.
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
BUG=chrome-os-partner:33728
TEST=build
Signed-off-by: Pawel Osciak <posciak@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/232582
Trybot-Ready: Tomasz Figa <tfiga@chromium.org>
Tested-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Wu-cheng Li <wuchengli@chromium.org>
Commit-Queue: Tomasz Figa <tfiga@chromium.org>
Conflicts:
include/uapi/linux/videodev2.h
Change-Id: I862bb5796e27bcbbd055e22202ac9a1ed0cc6f7d
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
The VOP DCLK is used to generate panel clocks.
For veyron, we have decided to permanently assign vop0 for
use with HDMI and vop1 for use with eDP.
Furthermore, to allow us to generate a wide range of precise pixel clocks,
we will be dedicating the NPLL exclusively for use as the parent clock
for VOP0/HDMI.
To implement the exclusive assignment of NPLL in the kernel, we remove
the NPLL entry from all clock muxes that would otherwise be able to select
it (such as vop1). For vop0, we remove all choices *except* NPLL.
Before booting the kernel, the bios will configure vop0 and vop1 as it
sees fit - potentially assigning NPLL to vop1 and some other PLL to vop0.
Thus, at boot it is possible that from the kernel's perspective, these
clocks are orphans. To fix this, we explicitly assign their clock parents
to ensure that they are properly parented no matter what state they are
when the kernel boots.
Change-Id: Iafe301abcbf211246fda66519cea5fc946af97ee
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Panel regulator is controller by a normal GPIO, so we need to
write a regulator-fixed node for it.
Change-Id: I24a0f2787ef3bb93422296e8a97c076040460ccc
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9201801/)
Panel regulator is controller by a normal GPIO, so we need to
write a regulator-fixed node for it.
Change-Id: I4368b16bf49ef04a539aad154f7c16b094bfc382
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9201803/)
The default eDP panel on RK3288 EVB board is LG LP079QX1-SP0V TFT LCD,
we haven't declared the panel regulator in the 'panel-simple' device
node here, so the specific board like ACT8846 / RK8080 need to support
the panel power supply.
Change-Id: Ibf4a6457d606027eaa91cacf6fde2241376afd13
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9201815/)
The AUO B101EW05 panel is a 10.1" 1280(RGB)x800 WXGA TFT-LCD panel,
connected using LVDS interfaces.
Change-Id: Ic80369353f5e1726d2ea2ace6d53bb2bcdae6fc2
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
The AUO B101EW05 panel is a 10.1" 1280(RGB)x800 WXGA TFT-LCD panel,
connected using LVDS interfaces
Change-Id: Ic67fe5793a975b585cecfb8da02e81cd9fa6346f
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Chunghwa CLAA070WP03 is 7” color TFT-LCD module composed of LCD
panel, LVDS driver ICs, control circuit and backlight. This module
supports 800x1280 mode.
Change-Id: I7f71464a80725d648802918740e64a0368f5c480
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Chunghwa CLAA070WP03 is 7” color TFT-LCD module composed of LCD panel,
LVDS driver ICs, control circuit and backlight. This module supports
800x1280 mode.
Change-Id: I6a6339ad25664e2e47fc0e0de5c079db3494bd25
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
vcc_wl and vcc_lcd are 2 gpio switches for rk3288-evb-act8846 board.
Change-Id: I49fc20665adf4176d672fdd3e4030ee472f558a8
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(cherry pick from commit 662513a14c)
The arm64 virtual addresses of kernel are like:
VA_START < MODULES_VADDR < KIMAGE_VADDR < PAGE_OFFSET.
PAGE_OFFSET is the virtual address of the start of the linear map.
And the vmalloc, kernel code and so on are between VA_START and
PAGE_OFFSET, so it is necessary to expand dump addresses to VA_START,
instead of PAGE_OFFSET.
Change-Id: I810ed216862de4c6e68b92d483de4aa68da532b8
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
I don't need send for upstream since the rockchip inside kernel
need it for tuning. At least the upstream can work it with dwmmc.
Change-Id: I73c12b455c7dc5320d6c06f9e29ddec5c4a6def5
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
We have the brother chipset that RK3228 and RK3229, they share most
of dts configuration, but there are a number of different features.
In order to develop the future when they are easy to distinguish,
we need them to be independent.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-armsoc/dts32 commit 8372d93df7)
Change-Id: I0b3c91cddb3ca919b165ba1ec5b2b9466945546d
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Only one of "broken-cd" and "non-removable" should be supplied
according to Documentation/devicetree/bindings/mmc/mmc.txt.
Obviously emmc and sdio-wifi are non-removable devices, while
broken-cd is for removable device whose card detect pin is broken.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-armsoc/dts32 commit 57375d88fa)
Change-Id: Ie8df62156fbc96c0c9e16d05389b2f230b261f0e
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This patch enables the tsadc for rk3228 evb board.
The rk3228 evb board uses the CRU to reset the chip since it hasn't the
PMIC to connect it, and TSHUT is low active on evb board.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-armsoc/dts32 commit 26f5e19dfb)
Change-Id: I12ce9b1e2fb2c740bef100a22d746d5e128253e6
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This patch adds the thermal needed main information for rk3228 SoCS.
Basically has the following content:
1) TSADC controller:
Add the needed attributes for rk3036 TSADC controller.
Especially for the TSHUT, in some cases if we are unable to shut it down
in orderly fashion (says: kernel is stuck holding a lock or similar), then
hardware TSHUT will reset it.
If the temperature is over 95C over a period of time the thermal shutdown
of the tsadc is invoked with can either reset the entire chip via the CRU,
or notify the PMIC via a GPIO. This should be set in the specific board.
2) Thermal zones:
Add the needed device mode for thermal generic framework.
Detail in Documentation/devicetree/bindings/thermal/thermal.txt.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-armsoc/dts32 commit 7796031eec)
Change-Id: I415d5ac7ba2bca2259821dae6af98970e039d455
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
There are old v3.10 dts and unsuitable for v4.4, we need to remove them.
Change-Id: I070fb1fd5d513883f43dfbdab6f173e68fe48e72
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
The rk3288 SoC has an option to switch all of the PWMs in the system
between the old IP block and the new IP block. The new IP block is
working and tested and the suggested PWM to use, so setup the SoC to
use it and then we can pretend that the other IP block doesn't exist.
This code could go lots of other places, but we've put it here. Why?
- Pushing it to the bootloader just makes the code harder to update in
the field. If we later find a bug in the new IP block and want to
change our mind about what to use we want it to be easy to update.
- Putting this code in the driver for IP block is a lot of extra work,
device tree bindings, etc. Now that the new IP block is validated
it's likely no future SoCs will need this code. Why pollute the PWM
driver with this? This is an rk3288 thing so it should be in rk3288
code.
- There's a single bit that switches over PWMs, which makes it extra
hard to put this under the PWM device tree nodes.
Change-Id: Ib178129fc4f24f71d3a6f7315f757f91b5bdf534
Signed-off-by: Doug Anderson <dianders@chromium.org>
