Rk3399 support single and burst mode, and flushp instruction.
But burst mode improve transfer efficiency.
Please refer to:
Commit 8e770f371c
"dmaengine: pl330: add burst mode according to dts config"
Change-Id: I2eb36723697cf548dc75aca0e5a276a86cd2419d
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Rk3366 support single and burst mode, and flushp instruction.
But burst mode improve transfer efficiency.
Please refer to:
Commit 8e770f371c
"dmaengine: pl330: add burst mode according to dts config"
Change-Id: I5e3fef4684f324dda015c0afd73535c062952fc1
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Because rk3368 pl330 dma controller doesn't support single
mode, so it is necessary to set peripherals-req-type-burst.
Please refer to:
Commit 8e770f371c
"dmaengine: pl330: add burst mode according to dts config"
Change-Id: I44de28cca0085bc3d8f25a5913dbb527c36d8f83
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Because rk3288 pl330 dma controller doesn't support single
mode, so it is necessary to set peripherals-req-type-burst.
Please refer to:
Commit 8e770f371c
"dmaengine: pl330: add burst mode according to dts config"
Change-Id: Ic972880807e858334a1df8fa3f9bb567a8078ff9
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Pl330 integrated in rk3368 platform doesn't support
DMAFLUSHP function. So we add arm,pl330-broken-no-flushp quirk
for it.
Change-Id: Ia7f4bb6ffa1fba01dac5ac2257499dbbc9887da6
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Pl330 integrated in rk3xxx platform doesn't support
DMAFLUSHP function. So we add arm,pl330-broken-no-flushp quirk
for it.
Change-Id: Ibea3bc46e460bf2cf6253e6cc1eea109f651163e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org next/linux-next.git master
commit 9bed8b41d8)
Pl330 integrated in rk3288 platform doesn't support
DMAFLUSHP function. So we add arm,pl330-broken-no-flushp quirk
for it.
Change-Id: I7ebd9fdd9b17b9a05e2ae859fab6b62f2967d9e5
Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Sonny Rao <sonnyrao@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org next/linux-next.git master
commit e7d6c9b116)
As the rk3036 only support the burst mode, so we need add it since
The commit 8e770f371c
"dmaengine: pl330: add burst mode according to dts config"
had been supported in kernel.
Change-Id: I074aa9a98c78a8ad8b1263a07690ffc2f8dfa718
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This patch is only here to be able to test provisioning of energy related
data from an arch topology shim layer to the scheduler. Since there is no
code today which deals with extracting energy related data from the dtb or
acpi, and process it in the topology shim layer, the content of the
sched_group_energy structures as well as the idle_state and capacity_state
arrays are hard-coded here.
This patch defines the sched_group_energy structure as well as the
idle_state and capacity_state array for the cluster (relates to sched
groups (sgs) in DIE sched domain level) and for the core (relates to sgs
in MC sd level) for a Cortex A7 as well as for a Cortex A15.
It further provides related implementations of the sched_domain_energy_f
functions (cpu_cluster_energy() and cpu_core_energy()).
To be able to propagate this information from the topology shim layer to
the scheduler, the elements of the arm_topology[] table have been
provisioned with the appropriate sched_domain_energy_f functions.
Change-Id: I8c014bbd04f6a1d57892be9bfa16affe07948dcf
cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
* lsk-v4.4-eas-v5.2:
DEBUG: schedtune: add tracepoint for schedtune_tasks_update() values
DEBUG: schedtune: add tracepoint for CPU boost signal
DEBUG: schedtune: add tracepoint for SchedTune configuration update
DEBUG: sched: add energy procfs interface
DEBUG: sched,cpufreq: add cpu_capacity change tracepoint
DEBUG: sched: add tracepoint for CPU load/util signals
DEBUG: sched: add tracepoint for task load/util signals
DEBUG: sched: add tracepoint for cpu/freq scale invariance
sched/fair: filter energy_diff() based on energy_payoff value
sched/tune: add support to compute normalized energy
sched/fair: keep track of energy/capacity variations
sched/fair: add boosted task utilization
sched/{fair,tune}: track RUNNABLE tasks impact on per CPU boost value
sched/tune: compute and keep track of per CPU boost value
sched/tune: add initial support for CGroups based boosting
sched/fair: add boosted CPU usage
sched/fair: add function to convert boost value into "margin"
sched/tune: add sysctl interface to define a boost value
sched/tune: add detailed documentation
fixup! sched/fair: jump to max OPP when crossing UP threshold
fixup! sched: scheduler-driven cpu frequency selection
sched: rt scheduler sets capacity requirement
sched: deadline: use deadline bandwidth in scale_rt_capacity
sched: remove call of sched_avg_update from sched_rt_avg_update
sched/cpufreq_sched: add trace events
sched/fair: jump to max OPP when crossing UP threshold
sched/fair: cpufreq_sched triggers for load balancing
sched/{core,fair}: trigger OPP change request on fork()
sched/fair: add triggers for OPP change requests
sched: scheduler-driven cpu frequency selection
cpufreq: introduce cpufreq_driver_is_slow
sched: Consider misfit tasks when load-balancing
sched: Add group_misfit_task load-balance type
sched: Add per-cpu max capacity to sched_group_capacity
sched: Do eas idle balance regardless of the rq avg idle value
arm64: Enable max freq invariant scheduler load-tracking and capacity support
arm: Enable max freq invariant scheduler load-tracking and capacity support
sched: Update max cpu capacity in case of max frequency constraints
cpufreq: Max freq invariant scheduler load-tracking and cpu capacity support
arm64, topology: Updates to use DT bindings for EAS costing data
sched: Support for extracting EAS energy costs from DT
Documentation: DT bindings for energy model cost data required by EAS
sched: Disable energy-unfriendly nohz kicks
sched: Consider a not over-utilized energy-aware system as balanced
sched: Energy-aware wake-up task placement
sched: Determine the current sched_group idle-state
sched, cpuidle: Track cpuidle state index in the scheduler
sched: Add over-utilization/tipping point indicator
sched: Estimate energy impact of scheduling decisions
sched: Extend sched_group_energy to test load-balancing decisions
sched: Calculate energy consumption of sched_group
sched: Highest energy aware balancing sched_domain level pointer
sched: Relocated cpu_util() and change return type
sched: Compute cpu capacity available at current frequency
arm64: Cpu invariant scheduler load-tracking and capacity support
arm: Cpu invariant scheduler load-tracking and capacity support
sched: Introduce SD_SHARE_CAP_STATES sched_domain flag
sched: Initialize energy data structures
sched: Introduce energy data structures
sched: Make energy awareness a sched feature
sched: Documentation for scheduler energy cost model
sched: Prevent unnecessary active balance of single task in sched group
sched: Enable idle balance to pull single task towards cpu with higher capacity
sched: Consider spare cpu capacity at task wake-up
sched: Add cpu capacity awareness to wakeup balancing
sched: Store system-wide maximum cpu capacity in root domain
arm: Update arch_scale_cpu_capacity() to reflect change to define
arm64: Enable frequency invariant scheduler load-tracking support
arm: Enable frequency invariant scheduler load-tracking support
cpufreq: Frequency invariant scheduler load-tracking support
sched/fair: Fix new task's load avg removed from source CPU in wake_up_new_task()
Conflicts:
drivers/cpufreq/Kconfig
include/linux/cpufreq.h
include/trace/events/power.h
Change-Id: I0efa846911ea6b8d3f458115529cf67be73858e3
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
Decreasing the use_count of urb is pended since core usb have put it
into the tasklet after HC dequeued, so we add a condition which check
urb in HC queue is NULL or not to enhance exception conditions here.
BUG=Redmine: Defect#95115
TEST=RK3366-SDK, LS mouse device works.
Change-Id: I8b6d8ae2a866817b0c638e0b43811d108962b591
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch add peripherals-req-type-burst property to PL330 DMA
controller nodes to enable dma burst mode when it is present.
Change-Id: I1b6923d9a23c15be800a5a1bd3f2161dd7b8826b
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Default is single mode, but some socs only support burst
mode. What's more, burst mode can improve memory accessing
efficiency.
In pl330 dts node:
Add peripherals_req_type_burst to enable burst mode.
Change-Id: I9c7ade28ef6901a746e53ee1cefeec55c8b24340
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
According to Synopsys Databook, we shouldn't be
relying on GCTL.CORESOFTRESET bit as that's only for
debugging purposes. Instead, let's use DCTL.CSFTRST
if we're OTG or PERIPHERAL mode.
Host side block will be reset by XHCI driver if
necessary. Note that this reduces amount of time
spent on dwc3_probe() by a long margin.
We're still gonna wait for reset to finish for a
long time (default to 1ms max), but tests show that
the reset polling loop executed at most 19 times
(modprobe dwc3 && modprobe -r dwc3 executed 1000
times in a row).
Change-Id: Ie268d8fbe41dbe31e0070556dfd204ad51453c2f
Suggested-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit f59dcab176)
Per dwc3 databook "Buffer Size Rules and Zero-Length Packets",
dwc3 needs buffer size to be aligned to MaxPacketSize on ep out.
Change-Id: Iff0e9c29c02c09b93bb34fed178051c02221ecc7
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
This patch doesn't fix any issue, but conforms
to linux coding style.
Change-Id: I87326a21594b905ea5791f73efc1cea0299abe4d
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
The FIFO resizing logic has been removed, and the default
Tx FIFO size is right on rk3399, so remove the property.
Change-Id: Id3cc138e07222d9256a5cc9b1c81a6d7523d05fb
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
That FIFO resizing logic was added to support OMAP5
ES1.0 which had a bogus default FIFO size. I can't
remember the exact size of default FIFO, but it was
less than one bulk superspeed packet (<1024) which
would prevent USB3 from ever working on OMAP5 ES1.0.
However, OMAP5 ES1.0 support has been dropped by
commit aa2f4b16f8 ("ARM: OMAP5: id: Remove ES1.0
support") which renders FIFO resizing unnecessary.
Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
(cherry picked from commit bc5081617f)
Conflicts:
drivers/usb/dwc3/core.h
Change-Id: Id10f41fd06e4877c46a8d760ba95155499a9f46d
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
The rk3399 clock table had a simple typo in it, calling the SDMMC sample
and drive clocks by the wrong name. Fix this minor typo.
Change-Id: I154f70bd98b58bf3cc148043b11e4a8d18203816
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Acked-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
(cherry picked from git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
commit 84752e8d8a)
The ARM GICv3 specification mentions the need for dsb after a read
from the ICC_IAR1_EL1 register:
4.1.1 Physical CPU Interface:
The effects of reading ICC_IAR0_EL1 and ICC_IAR1_EL1
on the state of a returned INTID are not guaranteed
to be visible until after the execution of a DSB.
Not having this could result in missed interrupts, so let's add the
required barrier.
[Marc: fixed commit message]
Change-Id: I45f64990252b17a9e89ef69f3e53261b6af62ced
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 1a1ebd5fb1)
I don't need send for upstream since the rockchip inside kernel
need it for tuning. At least the upstream can work it with dwmmc.
Change-Id: Ia9f0836624e8ef1df225dbc6ad1792ec4fb2abbd
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This patch add max burst capability for dmaengine and
limit burst capability to one for PL330_QUIRK_BROKEN_NO_FLUSHP
Change-Id: I378325508af1246177e327c6572611545c52e04e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
(cherry picked from git.kernel.org next/linux-next.git master
commit 86a8ce7d41)
This patch add max_burst to dma_get_slave_caps for clients
to get the burst capability of slave dma controller.
Conflicts:
include/linux/dmaengine.h
Change-Id: I7ffcf775ad48247ee0bfa9e18c8ee3b4b256eab2
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
(cherry picked from commit 6d5bbed30f)
