According to the dwc2 programmer's guide v3.10a, in '2.1.3.2 Dedicated
FIFO Mode with No Thresholding', it suggested that:
Device RxFIFO =
- Scatter/Gather DMA mode:
(4 * number of control endpoints + 6) + ((largest USB packet used / 4) +
1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK
on rockchip platforms:
(4 * 1 + 6) + ((1024 / 4) + 1) + (2 * 6) + 1 = 280
- Slave or Buffer DMA mode:
(5 * number of control endpoints + 8) + ((largest USB packet used / 4) +
1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK
on rockchip platforms:
(5 * 1 + 8) + ((1024 / 4) + 1) + (2 * 6) + 1 = 283
Device IN Endpoint TxFIFO =
The TxFIFO must equal at least one MaxPacketSize (MPS).
In addition to RxFIFO and TxFIFOs, refer to dwc2 databook v3.10a,
'Figure 2-13 Device Mode FIFO Address Mapping and AHB FIFO Access Mapping
(Dedicated FIFO)', it required that when the device is operating in non
Scatter Gather Internal DMA mode, the last locations of the SPRAM are used
to store the DMAADDR values for each Endpoint (1 location per endpoint).
When the device is operating in Scatter Gather mode, then the last locations
of the SPRAM store the Base Descriptor address, Current Descriptor address,
Current Buffer address, and status quadlet information for each endpoint
direction (4 locations per Endpoint). If an Endpoint is bidirectional , then
4 locations will be used for IN, and another 4 for OUT).
Considering that the total FIFO size of dwc2 otg is 0x3cc (972),
and we must reserve (4 * 13) = 52 locations for all Endpoints.
So reconfig dwc2 device fifo size as follows:
Device RxFIFO = 280
Device IN Endpoint TxFIFO
- FIFO #0 = (64 / 4) = 16 (Assuming this is used for EP0)
- FIFO #1 = (1024/4) = 256 (Assuming this is used for Isochronous)
- FIFO #2 = (512/4) = 128
- FIFO #3 = (512/4) = 128
- FIFO #4 = (256/4) = 64
- FIFO #5 = (128/4) = 32
- FIFO #6 = (64/4) = 16
After reconfig the dwc2 device fifo size, test mtp write on rockchip
platform (PC -> rockchip platform) on rk312x/rk3326/px30/rk3288 evb,
when mask the 'vfs_write' in f_mtp.c, the writing data rate can be
increased from 16MBps ~ 20MBps to 30MBps ~ 36MBps on different kinds
of rockchip evbs.
Change-Id: Icdf8a5dd95f96d174233e4ffc765c9a982b9f0b6
Signed-off-by: William Wu <william.wu@rock-chips.com>
Single entry is for target voltage and three entries are for
<target min max> voltages. Change cpu opp-microvolt form one entry to
three entries and set maximum acceptable voltage to a high value so that
regulator device can supply multiple consumers at the same time.
Fixes: 16e9353f89 ("arm: dts: rockchip: Change cpu opp-microvolt form one entry to three")
Change-Id: I96e5f87f2945e63e8f4a073fa0292f001830b13c
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
The vdd_logic is a pwm regulator. Since '#pwm-cells = <2>', there
is not polarity invert support by pwm driver, so we have to add
property 'pwm-dutycycle-range = <100 0>' to support polarity invert
by pwm regulator driver itself.
Change-Id: Ie5d2cda67ce19dc792f96263836bab658d385681
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Add supports-emmc for emmc; supports-sd for sdcard; supports-sdio for
wifi.
Change-Id: I13d3918f41f63ed9b27e9969e6f89d1006c9d45c
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Serial Flash controller is used to control the data
transfer between this SoC and a serial nor or nand
flash device.
Change-Id: Ibe7c8c4a11410287c34c1a7dc5b232b330ee6751
Signed-off-by: Randy Li <randy.li@rock-chips.com>
The vpu qos registers need to save and restore when reset.
Change-Id: I649cf4a360842ad1abb06c35a6fd8d3868fbf706
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
According to the actual schematic designed by kylin board, update and
rename the regulators for rk808 node information.
Especially gpu regulator voltage, the schematic didn't have this
regulator, this regulaor should be applied by cpu regulator since the
cpu/gpu/ddr are belong to the same logic power supply.
Change-Id: I39e4cf18969391da396cc775f8660701e42977bd
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
As the vpu needed handle the power domain for reset function, this patch
supported the vpu domain for rk3036 Socs.
Change-Id: I67ad6085e2eb9a213c364d58713f02cc78ce6849
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
rk3036 doesn't support vdd_arm power supply off when system suspend.
Change-Id: I46bd8a7c2b672be30d8106b867275e8ba7d77e54
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
As the HDMI-audio/codec will cause the hang on bootup, the root
cause that kylin get the invalid master clock from i2s.
$cat/sys/kernel/debug/clk/clk_summary
..
i2s_pre 0 0 0 0 0
sclk_i2s 0 0 0 0 0
i2s_clkout 0 0 0 0 0
Since i2s clock selects io input clock by default, but the hardware
didn't supply the clock.
This patch will fix the sclk_i2s's parent on i2s_frac.
As following:
$cat/sys/kernel/debug/clk/clk_summary
..
i2s_src 1 1 594000000 0 0
i2s_frac 1 1 22579200 0 0
i2s_pre 2 2 22579200 0 0
sclk_i2s 1 1 22579200 0 0
As far, the audio can work with aplay/record on kylin.dts
Says:
(aplay /dev/urandom)
/* recording */
arecord -f cd -d 10 /tmp/audio.wav
/* playback */
aplay /tmp/audio.wav
Change-Id: I73534a0d763eb02fb55e000ce068d9d604bf20ed
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
As the cpu frequency is less than 816MHz, the HDMI display maybe
probably cause a flower screen as below log[0]. And Kylin used the rk3036g
series SoCs that the max cpu frequency supported the 1GHz, not 1.2GHz.
In a word, keep the cpu frequency to 1GHz for kylin board.
log[0]:
[26.498843] rk_iommu 10118300.iommu: Enable stall request timed out,
status: 0x000011
[26.528809] rk_iommu 10118300.iommu: Disable paging request timed out,
status: 0x000011
[26.598849] rk_iommu 10118300.iommu: Enable stall request timed out,
status: 0x000011
[26.607579] rockchip-vop 10118000.vop: Failed to attach iommu device
[26.614916] rockchip-vop 10118000.vop: failed to attach dma mapping, -110
..
Change-Id: I8e1d4527b649d8857a9d80a121c10935a4cd1030
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
As the emmc is supplyed power by vcc_io, that's 3.3v voltage.
the default 1.8v volatge will cause the emmc error. as the following:
[ 17.096082 ] mmcblk1: error -115 sending stop command, original cmd
response 0x900, card status 0xb00
[ 17.127022 ] mmcblk1: error -110 transferring data, sector 664720, nr
72, cmd response 0x900, card status 0xb00
Remove the mmc-ddr-1_8v to keep the default the 3.3v voltage.
Change-Id: I9e2539d63fd93e72d9febbb311fbd686c5a11d09
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This patch supported the gpu opp table for rk3036.
The gpu clock's parent is DPLL, the default frequency is 400MHz, we need
assign 400MHz for gpu to be better working.
There is a quickly way for testing the gpu scaling frequency.
As following:
"
unset FREQS
read -a FREQS < /sys/class/devfreq/10091000.gpu/available_frequencies
RANDOM=$$$(date +%s)
while true; do
echo userspace > /sys/class/devfreq/10091000.gpu/governor
FREQ=${FREQS[$RANDOM % ${#FREQS[@]} ]}
echo GPU:Now ${FREQ}
echo ${FREQ} > /sys/class/devfreq/10091000.gpu/userspace/set_freq
sleep 1
done
"
Change-Id: Ia8eb3074e457014c497338a0a129551c51450104
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This patch supported the cpu voltage by changed with different
frequency, otherwise we will hit the following error on bootup.
..
[ 5.031516] cpu cpu0: Failed to get cpu_reg
[ 5.047725] cpu cpu0: clk or regulater is unavailable
..
Also, remove the 408M and 600M for rk3036 board, as the pclk_hdmi's parent
on apll, the low frequency will make the pclk be bad for hdmi display.
Change-Id: Ia4aac76a08cad3a59c33cd81065f943201a23a35
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This patch fixes the BT power reported the failure message.
As following:
root@linaro-alip:~# echo 1 > /sys/class/rfkill/rfkill0/state
[ 892.558269] rockchip-pinctrl pinctrl: pin gpio0-19 already requested
by 20060000.serial; cannot claim for wireless-bluetooth
[ 892.571052] rockchip-pinctrl pinctrl: pin-19 (wireless-bluetooth) status -22
...
And for now, the BT can work with this patch.
root@linaro-alip:~# echo 1 > /sys/class/rfkill/rfkill0/state
[ 69.328768] [BT_RFKILL]: ENABLE UART_RTS
[ 69.438540] [BT_RFKILL]: DISABLE UART_RTS
[ 69.443117] [BT_RFKILL]: bt turn on power
...
root@linaro-alip:~# hcitool dev
Devices:
hci0 94:A1:A2:E9:2D:18
And
root@linaro-alip:~# bluetoothctl
[NEW] Controller 94:A1:A2:E9:2D:18 linaro-alip [default]
[bluetooth]# scan on
Discovery started
[CHG] Controller 94:A1:A2:E9:2D:18 Discovering: yes
..
Change-Id: I2148f4203300ab4265fd3ba718f0d3ec0c57e7ca
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
It allows me to set the mac address in the bootloader.
Change-Id: Iad988205c6953e843e62aec67daad52128086324
Signed-off-by: Randy Li <randy.li@rock-chips.com>
There is a combo of a HEVC decoder and a VPU1 decoder at rk3036.
Change-Id: Ia7174cc9e2f2d640a74271077bd62cc68f3482b4
Signed-off-by: Randy Li <randy.li@rock-chips.com>
In order to save power and improve the performance, we can add the opp
table for rk3036 SoCs.
Also, make sure the codec works happily, we should ensure the arm/logic
voltage is greater than 1v.
Change-Id: I9aa17be547eb21e5a83c09780356436c3075bae6
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
In order to support the ap6212 module with rockchip wlan driver,
the kylin dts has to change the below for working.
1) We should add the 'supports-sdio' property for mmc tuning,
that's the rockchip private property, not on the upstream.
2) We should add the wifi power control pin and wifi/bt data for dts,
Maybe the history issue, they like the old driver for power
contronlling, the upstream didn't need these for working. we should
remove it in the future.
Change-Id: Id49de7ad77b8658a551a07659a8a2ddc9691874c
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
As the inno-hdmi driver introduced this clock, add it for dts supporting.
Change-Id: I43328a25f0ac72d5a5b7631cc8ff6ce98b78669a
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
In rk3036, the voltages of CPU and GPU are controlled by the same
regulator 'vdd_cpu'.
Here, we fix it to 1.25v to ensure that GPU could work well in
development period.
The actual voltage GPU needs might be much lower, and relative to
the frequence GPU runs at. this would be optimized when we implement
GPU DVFS with devfreq.
Change-Id: Ia25f0a67577fbfe248a25e4d913dc5f14fa40f0d
Signed-off-by: chenzhen <chenzhen@rock-chips.com>
