Since the new IP has expanded the maximum hwlock user count to 6 bits,
this adds configuring the maximum hwlock user count via dtsi/dts to
support the feature.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I6e59bb22984e6ee5c9d31099266778c0e42350bf
Set the maximum user count via the "rockchip,hwlock-max-user" property
to indicate the maximum number of users supported by this IP.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I7dff4c813346db94642ed5b36191af0a1c0e5041
This helper will be responsible for reading and parsing our
properties. No functional changes in this patch, cleanup only.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I8476a5f4d3e78f90d9749fd949ff5287eb400558
As of Mailbox Version 2.2.0, a version register and a channel lock
function have been added, and this change is intended to provide
support for these features.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: Ie4778dc5860fbb7f2f55c36a4c4f1b6fc97b1c99
Add the regulator-settling-time-up-us configuration in the PWM
regulator to ensure sufficient time for the voltage to reach a
stable state during the rising phase.
Signed-off-by: Shengfei Xu <xsf@rock-chips.com>
Change-Id: I2ec7255931f22c1f8c46e41fac34b2c215e9abf3
According to DP1.4a 5.3.3, To support more feature active protocol
converte adapters. All the adapters are branch device, Read the
Detailed Capabilities Info to get the branch type and the feature
it support. For Example, the max dot clock for VGA, max TDMS clock
for HDMI, the YCbCr420 support or not for HDMI 2.0, conversion to
YCbCr420 from YCbCr444 or not for HDMI 2.0.
According the feature of branch device, filter the resolution, color
format and color depth that the branch device can't support.
Change-Id: I640ce0e6324811875a9dabea846514bc3e42f915
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
As SPARSE_SPLIT_SIZE_16x16 afbc format each sub block size is
16*8*4=512 Byte, This can make DDR each channel keep balanced.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I1aa7a4c6068fec80f144979dca821bf9cc534b6a
According to commit fdcfd85433 ("rtc: rework rtc_register_device() resource management").
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: If37750a01675a5d5e2b9231d1549e70bc349a3e7
For special scenarios, such as after the PCIe PHY is bifurcation and
with different usage like phy1 is the RC and the other phy0 is the EP.
Since the EP has been initialized in the previous stage, it is not
expected that repeated initialization in the kernel stage will cause
the link to be disconnected. Therefore, no matter which of the two
controllers performs initialization, the PHY re-initialization operation
should be avoided.
Change-Id: I7c04b537b18020d434d14049c5a0661739713265
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Configure which pin controls the shutdown function via the
shutown_by_pwrctrln property in the DTS.
Change-Id: I7bb3adf28ff7e93fd318d08274cb88271b925027
Signed-off-by: Shengfei Xu <xsf@rock-chips.com>
According to the CEA-861 specification, when the RGB default color gamut is detected:
When the VIC is between 2 and 127, it is CE video, i.e., limited range.
When the VIC is any other value, it is IT video, i.e., full range.
Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>
Change-Id: I258bd84096a340fd88e37e7f127301469baadef9
If the RK806M DVS mode does not follow the configured timing sequence,
it may cause abnormal power-off.
The settings must be configured in the following order:
entering voltage adjustment:
first configure SLPn_FUN, then configure XXX_SLP_CTR_SEL at addresses 0x64~0x6e.
exiting voltage adjustment:
first clear XXX_SLP_CTR_SEL at addresses 0x64~0x6e to 0, then modify SLPn_FUN.
Change-Id: I265d916b99160fddf467f7c12149490a95f75ca8
Signed-off-by: Shengfei Xu <xsf@rock-chips.com>
