Ethernet device cannot be detected on warm boot sometimes. This patch is
to add the power reset routines for ethernet device using PMIC. Then
ethernet device can be reset hardware-wise.
Change-Id: Iffbe2966da7e4679f63b91ab79241167391792df
Signed-off-by: Brian Kim <brian.kim@hardkernel.com>
Signed-off-by: Marian Mihailescu <mihailescu2m@gmail.com>
Added .shutdown function to s2mps11 to help poweroff the board successfully.
The device driver clears the register to turn off the PMIC.
s2mps11-pmic: S2MPS11_REG_CTRL1 reg value 16:00000000000000000000000000010000
Console log.
* Unmounting temporary filesystems... [ OK ]
* Deactivating swap... [ OK ]
* Unmounting local filesystems... [ OK ]
* Will now halt
[ 209.020280] reboot: Power down
[ 209.122039] Power down failed, please power off system manually.
Change-Id: If6ea0dec154b00ceeaaddbac393c67dc35c26279
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: memeka <mihailescu2m@gmail.com>
Signed-off-by: Marian Mihailescu <mihailescu2m@gmail.com>
Commit 4294a779bd ("PM / devfreq: exynos-bus: Convert to use
dev_pm_opp_set_rate()") introduced errors:
exynos-bus: new bus device registered: soc:bus_wcore ( 84000 KHz ~ 400000 KHz)
exynos-bus: new bus device registered: soc:bus_noc ( 67000 KHz ~ 100000 KHz)
exynos-bus: new bus device registered: soc:bus_fsys_apb (100000 KHz ~ 200000 KHz)
...
exynos-bus soc:bus_wcore: dev_pm_opp_set_rate: failed to find current OPP for freq 532000000 (-34)
exynos-bus soc:bus_noc: dev_pm_opp_set_rate: failed to find current OPP for freq 111000000 (-34)
exynos-bus soc:bus_fsys_apb: dev_pm_opp_set_rate: failed to find current OPP for freq 222000000 (-34)
They are caused by incorrect PLL assigned to clock source, which results
in clock rate outside of OPP range. Add workaround for this in
exynos_bus_parse_of() by adjusting clock rate to those present in OPP.
Fixes: 4294a779bd ("PM / devfreq: exynos-bus: Convert to use dev_pm_opp_set_rate()")
Change-Id: Ic07e2d68e0da2efa07cb81cc9b4f76d8ad15bd76
Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Kamil Konieczny <k.konieczny@partner.samsung.com>
Signed-off-by: memeka <mihailescu2m@gmail.com>
The Adaptive Supply Voltage (ASV) driver adjusts CPU cluster operating
points depending on exact revision of an SoC retrieved from the CHIPID
block or the OTP memory. This allows for some power saving as for some
CPU clock frequencies we can lower CPU cluster's supply voltage comparing
to safe values common to all the SoC revisions.
This patch adds support for Exynos5422/5800 SoC, it is partially based
on code from https://github.com/hardkernel/linux repository,
branch odroidxu4-4.14.y, files: arch/arm/mach-exynos/exynos5422-asv.[ch].
Tested on Odroid XU3, XU4, XU3 Lite.
Change-Id: I1cfc9324ba11a77ebccbca1176caa28abb2527de
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: memeka <mihailescu2m@gmail.com>
This patch adds documentation of new optional "samsung,asv-bin"
property in the chipid device node and documents requirement of
"syscon" compatible string. These additions are needed to support
Exynos ASV (Adaptive Supply Voltage) feature.
Change-Id: Ib51dbc3ad36705abc3df17a6b80a614a0b28c215
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: memeka <mihailescu2m@gmail.com>
On some SoCs the Adaptive Voltage Scaling (AVS) technique is
employed to optimize the operating voltage of a device. At a
given frequency, the hardware monitors dynamic factors and either
makes a suggestion for how much to adjust a voltage for the
current frequency, or it automatically adjusts the voltage
without software intervention. Add an API to the OPP library for
the former case, so that AVS type devices can update the voltages
for an OPP when the hardware determines the voltage should
change. The assumption is that drivers like CPUfreq or devfreq
will register for the OPP notifiers and adjust the voltage
according to suggestions that AVS makes.
This patch is derived from [1] submitted by Stephen.
[1] https://lore.kernel.org/patchwork/patch/599279/
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
[s.nawrocki@samsung.com: added handling of OPP min/max voltage]
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: memeka <mihailescu2m@gmail.com>
Change-Id: I172ca9d88d40e97216eeac76ba3e74f12f984765
Convert Samsung Exynos Chipid bindings to DT schema format using
json-schema.
Change-Id: Ia6906a3f50d6f0a791fdd3e6e583e92a08716e4b
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: memeka <mihailescu2m@gmail.com>
The Exynos5422 SoC used on Odroid XU3 Lite boards belongs to
a special ASV bin but this information cannot be read from the
CHIPID block registers. Add samsung,asv-bin property for XU3
Lite to ensure the ASV bin is properly determined.
Change-Id: I6e977b9cf0829be7ffff5aa84d7ee6b3e65b49cd
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: memeka <mihailescu2m@gmail.com>
The CHIP ID block in addition to exact chip revision information
contains data and control registers for ASV (Adaptive Supply Voltage)
and ABB (Adaptive Body Bias). Add "syscon" compatible so the CHIPID
block can be shared by respective drivers.
Change-Id: Id7469143417eac92f1f7d010004b67ae6ed35e8d
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: memeka <mihailescu2m@gmail.com>
After adding the interrupt properties to Exynos5422 DMC bindings
example, the mapped memory region must be big enough to access
performance counters registers.
Fix also syntax errors (semicolons) and adjust indentation.
Change-Id: Ibbf0579f8aa76c56d9cee48809ed341e3561d383
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Lukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: memeka <mihailescu2m@gmail.com>
Introduce a new interrupt driven mechanism for managing speed of the
memory controller. The interrupts are generated due to performance
counters overflow. The performance counters might track memory reads,
writes, transfers, page misses, etc. In the basic algorithm tracking
read transfers and calculating memory pressure should be enough to
skip polling mode in devfreq.
Change-Id: Idb5deaa423d75a9a0961b64f9f9514d6ce7c95c1
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: memeka <mihailescu2m@gmail.com>
There is a need to access registers at address offset near 0x10000.
These registers are private DMC performance counters, which might be used
as interrupt trigger when overflow. Potential usage is to skip polling
in devfreq framework and switch to interrupt managed bandwidth control.
Change-Id: Iba1fd2397507b313f190e9232f0fab791fc28a3a
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: memeka <mihailescu2m@gmail.com>
Add interrupt to Dynamic Memory Controller in Exynos5422 and Odroid
XU3-family boards. It will be used instead of devfreq polling mode
governor. The interrupt is connected to performance counters private
for DMC, which might track utilisation of the memory channels.
Change-Id: I2b4680ff82a7ff2fc038196c197c85f33b258359
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: memeka <mihailescu2m@gmail.com>
Add description for optional interrupt lines. It provides a new operation
mode, which uses internal performance counters interrupt when overflow.
This is more reliable than using default polling mode implemented in
devfreq.
Change-Id: I3be940bc4d49620cd63287c8be8ccf6f73ba3d24
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: memeka <mihailescu2m@gmail.com>
Add compatible for Samsung k3qf2f20db LPDDR3 memory bindings.
Suggested to based on at25.txt compatible section.
Introduce minor fixes in the old documentation.
Change-Id: I48f8025c745f95cbd4b29cf2ad04d77cac685a1f
Suggested-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: memeka <mihailescu2m@gmail.com>
Fix issues captured by static checkers: used kfree() and missing 'static'
in the private function.
Fixes Smatch warning:
drivers/memory/samsung/exynos5422-dmc.c:272
exynos5_init_freq_table() warn: passing devm_ allocated variable to kfree. 'dmc->opp'
Fixes Sparse warning:
drivers/memory/samsung/exynos5422-dmc.c:736:1:
warning: symbol 'exynos5_dmc_align_init_freq' was not declared.
Change-Id: I98f7b908abc26f17187c771f668b7bf64658be38
Reported-by: kbuild test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: memeka <mihailescu2m@gmail.com>
Enable driver for Exynos5422 Dynamic Memory Controller supporting
dynamic frequency and voltage scaling in Exynos5422 SoCs.
Change-Id: Ib31c2789a5a87823a5441d922f3aec5c8696e187
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: memeka <mihailescu2m@gmail.com>
Add description of Dynamic Memory Controller and PPMU counters.
They are used by exynos5422-dmc driver.
There is a definition of the memory chip, which is then used during
calculation of timings for each OPP.
The algorithm in the driver needs these two sets to bound the timings.
Change-Id: Icd26d77033c2e1e4e71f28e64f5b126d865bdbbc
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: memeka <mihailescu2m@gmail.com>
In order to get the clock by phandle and use it with regmap it needs to be
compatible with syscon. The DMC driver uses two registers from clock
register set and needs the regmap of them.
Change-Id: I5f844e15214928b1b2240c4df9802a1924f207d3
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: memeka <mihailescu2m@gmail.com>
This patch adds driver for Exynos5422 Dynamic Memory Controller.
The driver provides support for dynamic frequency and voltage scaling
for DMC and DRAM. It supports changing timings of DRAM running with
different frequency. There is also an algorithm to calculate timigns
based on memory description provided in DT.
The patch also contains needed MAINTAINERS file update.
Change-Id: I6b81edf71772f9dd8ed3fde27b64cba9bbb29042
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: memeka <mihailescu2m@gmail.com>
The patch adds description for DT binding for a new Exynos5422 Dynamic
Memory Controller device.
Change-Id: I50cc19ae01d34bd30890e0dc65bf741bc5bc0aad
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: memeka <mihailescu2m@gmail.com>
The patch adds AC timings information needed to support LPDDR3 and memory
controllers. The structure is used in of_memory and currently in Exynos
5422 DMC. Add parsing data needed for LPDDR3 support.
It is currently used in Exynos5422 Dynamic Memory Controller.
Change-Id: I42ab5749c048f38a6e64c8ce401311228de87c93
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: memeka <mihailescu2m@gmail.com>
Specifies the AC timing parameters of the LPDDR3 memory device.
Change-Id: I05b121fb8eaa682afd88d383e38a9cfe9f6fa175
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: memeka <mihailescu2m@gmail.com>
Change directory name to be ready for new types of memories.
Change-Id: If95f444fbca82d0735402e3427d14870ac9dc169
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: memeka <mihailescu2m@gmail.com>
1. Each A15 cores thermal sensor now correctly used and will trigger the
fan or passive throttling as required.
2. Separate file used for trip points to allow unique labels per trip
per cpu to be generated without having to duplicate the trips each time.
Keeps code clear and allows for easy changes.
3. Trip points tweaked to optimise performance. A7's kept at full speed
for longer since they contribute little to the thermal load. Efficiency
is improved by not throttling them until required. A15's throttled
earlier to manage performance better under heavy loads to extract
maximum performance from the available cooling.
4. Cooling levels and temperature trip points tweaked by memeka
Change-Id: I5353daa395ed5234dc955eab036956855e952ce0
This patch adds support irq mode in trip point.
When that flag is set in DT, there is no need for polling
in thermal framework. Crossing the trip point will rise an IRQ.
The naming convention for tip point 'type' can be confussing
and 'passive' (whic is passive cooling) might be interpretted wrongly.
This mechanism prevents from missue and adds explicit setting
for hardware which support interrupts for pre-configured temperature
threshold.
Change-Id: I2ee4c318bc74c07bfc3654ac9f3d6de4f2142088
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: Eduardo Valentin <edubezval@gmail.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: memeka <mihailescu2m@gmail.com>
Add device tree node for Mali GPU for Exynos 542x SoC.
GPU is disabled by default, and is enabled for each board after the
regulator is defined. Tested on Odroid-XU4.
Change-Id: I902932d29c7093b666fa3a8a8e1d0fda8fb11d5c
Signed-off-by: Marian Mihailescu <mihailescu2m@gmail.com>
All top clocks on G3D path has to be enabled all the time to allow proper
G3D power domain operation. This is achieved by adding CRITICAL flag to
"mout_sw_aclk_g3d" clock, what keeps this clock and all its parents
enabled.
This fixes following imprecise abort issue observed on Odroid XU3/XU4
after enabling Panfrost driver by commit 1a5a85c564 "ARM: dts: exynos:
Add Mali/GPU node on Exynos5420 and enable it on Odroid XU3/4"):
panfrost 11800000.gpu: clock rate = 400000000
panfrost 11800000.gpu: failed to get regulator: -517
panfrost 11800000.gpu: regulator init failed -517
Power domain G3D disable failed
...
panfrost 11800000.gpu: clock rate = 400000000
8<--- cut here ---
Unhandled fault: imprecise external abort (0x1406) at 0x00000000
pgd = (ptrval)
[00000000] *pgd=00000000
Internal error: : 1406 [#1] PREEMPT SMP ARM
Modules linked in:
CPU: 7 PID: 53 Comm: kworker/7:1 Not tainted 5.4.0-rc8-next-20191119-00032-g56f1001191a6 #6923
Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
Workqueue: events deferred_probe_work_func
PC is at panfrost_gpu_soft_reset+0x94/0x110
LR is at ___might_sleep+0x128/0x2dc
...
[<c05c231c>] (panfrost_gpu_soft_reset) from [<c05c2704>] (panfrost_gpu_init+0x10/0x67c)
[<c05c2704>] (panfrost_gpu_init) from [<c05c15d0>] (panfrost_device_init+0x158/0x2cc)
[<c05c15d0>] (panfrost_device_init) from [<c05c0cb0>] (panfrost_probe+0x80/0x178)
[<c05c0cb0>] (panfrost_probe) from [<c05cfaa0>] (platform_drv_probe+0x48/0x9c)
[<c05cfaa0>] (platform_drv_probe) from [<c05cd20c>] (really_probe+0x1c4/0x474)
[<c05cd20c>] (really_probe) from [<c05cd694>] (driver_probe_device+0x78/0x1bc)
[<c05cd694>] (driver_probe_device) from [<c05cb374>] (bus_for_each_drv+0x74/0xb8)
[<c05cb374>] (bus_for_each_drv) from [<c05ccfa8>] (__device_attach+0xd4/0x16c)
[<c05ccfa8>] (__device_attach) from [<c05cc110>] (bus_probe_device+0x88/0x90)
[<c05cc110>] (bus_probe_device) from [<c05cc634>] (deferred_probe_work_func+0x4c/0xd0)
[<c05cc634>] (deferred_probe_work_func) from [<c0149df0>] (process_one_work+0x300/0x864)
[<c0149df0>] (process_one_work) from [<c014a3ac>] (worker_thread+0x58/0x5a0)
[<c014a3ac>] (worker_thread) from [<c0151174>] (kthread+0x12c/0x160)
[<c0151174>] (kthread) from [<c01010b4>] (ret_from_fork+0x14/0x20)
Exception stack(0xee03dfb0 to 0xee03dff8)
...
Code: e594300c e5933020 e3130c01 1a00000f (ebefff50).
---[ end trace badde2b74a65a540 ]---
In the above case, the Panfrost driver disables G3D clocks after failure
of getting the needed regulator and return with -EPROVE_DEFER code. This
causes G3D power domain disable failure and then, during second probe
an imprecise abort is triggered due to undefined power domain state.
Fixes: 45f10dabb5 ("clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path")
Fixes: c9f7567aff ("clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Change-Id: Ic999b9c06b43a3fa148ab254ccef518cecc99460
Signed-off-by: Marian Mihailescu <mihailescu2m@gmail.com>
Add CLK_SET_RATE_PARENT flag to all clocks on the path from VPLL to G3D,
so the G3D MALI driver can simply adjust the rate of its clock by doing
a single clk_set_rate() call, without the need to know the whole clock
topology in Exynos542x SoCs.
Change-Id: I0506b4cf9c5318ee8d16a5122a21e0bf8ad20e62
Suggested-by: Marian Mihailescu <mihailescu2m@gmail.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: memeka <mihailescu2m@gmail.com>
If streaming is active when the MFC device is closed, it will generate an IOMMU page-fault.
Change-Id: Ie5c664ecddaebedf282eae1d56e82821b5883ffd
Signed-off-by: memeka <mihailescu2m@gmail.com>
DMA allocations for MMAP type are uncached by default. But for
some cases, CPU has to access the buffers. ie: memcpy for format
converter. Supporting cacheable MMAP improves huge performance.
This patch enables cacheable memory for DMA coherent allocator in mmap
buffer allocation if non-consistent DMA attribute is set and kernel
mapping is present. Even if userspace doesn't mmap the buffer, sync
still should be happening if kernel mapping is present.
If not done in allocation, it is enabled when memory is mapped from
userspace (if non-consistent DMA attribute is set).
Change-Id: I1e8e65086a2e4511563e8e7c3748d3b5403f18c3
Signed-off-by: Heng-Ruey Hsu <henryhsu@chromium.org>
Tested-by: Heng-ruey Hsu <henryhsu@chromium.org>
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
Signed-off-by: memeka <mihailescu2m@gmail.com>
This patch moves vb2_dc_get_base_sgt() function above mmap buffers
callbacks, particularly vb2_dc_alloc() and vb2_dc_mmap() from where it
will be called for cacheable MMAP support introduced in the next patch.
Change-Id: Ia504fbc1f0b3741986e8fff1ad329215b6e2db2e
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
Signed-off-by: memeka <mihailescu2m@gmail.com>
