At MOS environment, the irq handle may be triggered immediately
after request irq, the irq handle maybe access vop2 memory, e.g.,
vop3_vp_isr() -> vop2_wb_handler() access vop2->wb->regs, so move
devm_request_irq() to the end of this function to make sure vop2 is
initialized.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I3df1cc08069ffcffefa91a523db75fb67cd47de3
This reverts commit 0cbdc8c1da.
The legacy glue layer driver dwc3-rockchip-inno.c is only
used for RK3328/RK3228H platforms, and now they use the
dwc3 core driver instead of the legacy driver, so let's
discard the legacy driver.
Change-Id: Ib1f43aacddea0e0155aa75b0efb58452b0514860
Signed-off-by: William Wu <william.wu@rock-chips.com>
The requirements of rk3506 codec are mainly divided into three
sampling rate groups: 48/44.1/32kHz.
And, the rk3506 codec has internal frequency division, the driver
limits these three mclk inputs:
#define MCLK_REFERENCE_8000 32768000
#define MCLK_REFERENCE_11025 45158400
#define MCLK_REFERENCE_12000 49152000
Therefore, it is necessary to add the "rockchip,mclk-no-set" property
to the SAI4 to avoid switching the mclk frequency in the function of
rockchip_sai_set_sysclk() after the codec configures mclk, causing
the codec filter to work abnormally.
Change-Id: Ic6cd0688287eb4c92c3b27bba4f60c46610c9006
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Sometimes the mclk frequency needs to be set by the external codec
according to the sampling rate, rather than just keeping a fixed
multiple of the sampling rate. In this case, through the property
of "rockchip,mclk-no-set", the SAI will not modify the mclk frequency
again after the codec sets it.
Change-Id: I9bacebb397b9219b773b9953afabd1c5156c8a19
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This patch removes the two uncommon sampling rates of 12000 and 24000Hz,
because they are not in the definition of SNDRV_PCM_RATE_8000_192000 in
the sound framework:
...
#define SNDRV_PCM_RATE_11025 (1U<<2) /* 11025Hz */
#define SNDRV_PCM_RATE_16000 (1U<<3) /* 16000Hz */
#define SNDRV_PCM_RATE_22050 (1U<<4) /* 22050Hz */
#define SNDRV_PCM_RATE_32000 (1U<<5) /* 32000Hz */
...
According to the configuration of the sampling rate group clock, the
configuration of 11025 and 22050Hz is added. And, it is changed to
select the appropriate mclk in the coeff_clk array according to the
sampling by the codec by default. If you need to use the previous
fixed FS method, you need to specify the property "rockchip,mclk-fs-fixed"
in the dts node.
Change-Id: Iae4478b807f4e6eb88bf6cc9f431ce2f725a5b36
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
In RK3576, DP0 attach to VP1 or VP2 will cause vertical stripe. It
need reset dclk after config stream output to avoid this issue.
Change-Id: I00112e8541828ed53a2ea91e7d79f8d148a7b3df
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Use devm_ioremap to get rid of the sram driver dependency.
Change-Id: I908c4f6aee1d545d80b5821375d0962c2640c0e2
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Since the iomux type for GPIO2-B has been fixed to IOMUX_WIDTH_2BIT, the
registers for pins 8 to 14 can now be calculated correctly. Therefore,
pins 8 to 14 have been removed from rk3328_mux_recalced_data.
Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Change-Id: I0af399d1fed813934e753bd08842b2ab182dce92
This is the 6.1.115 stable release
* tag 'v6.1.115': (2780 commits)
Linux 6.1.115
xfrm: validate new SA's prefixlen using SA family when sel.family is unset
arm64/uprobes: change the uprobe_opcode_t typedef to fix the sparse warning
ACPI: PRM: Clean up guid type in struct prm_handler_info
platform/x86: dell-wmi: Ignore suspend notifications
ASoC: qcom: Fix NULL Dereference in asoc_qcom_lpass_cpu_platform_probe()
net: phy: dp83822: Fix reset pin definitions
serial: protect uart_port_dtr_rts() in uart_shutdown() too
selinux: improve error checking in sel_write_load()
drm/amd/display: Disable PSR-SU on Parade 08-01 TCON too
hv_netvsc: Fix VF namespace also in synthetic NIC NETDEV_REGISTER event
xfrm: fix one more kernel-infoleak in algo dumping
LoongArch: Get correct cores_per_package for SMT systems
ALSA: hda/realtek: Add subwoofer quirk for Acer Predator G9-593
KVM: arm64: Don't eagerly teardown the vgic on init error
KVM: nSVM: Ignore nCR3[4:0] when loading PDPTEs from memory
openat2: explicitly return -E2BIG for (usize > PAGE_SIZE)
nilfs2: fix kernel bug due to missing clearing of buffer delay flag
ACPI: button: Add DMI quirk for Samsung Galaxy Book2 to fix initial lid detection issue
ACPI: PRM: Find EFI_MEMORY_RUNTIME block for PRM handler and context
...
Change-Id: Iee600c49a5c914b79141c62cda38e787e429a167
Conflicts:
arch/arm64/boot/dts/rockchip/rk356x.dtsi
drivers/gpio/gpio-rockchip.c
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
drivers/media/i2c/imx335.c
drivers/pci/controller/dwc/pcie-dw-rockchip.c
drivers/spi/spi-rockchip.c
drivers/spi/spidev.c
drivers/usb/dwc3/gadget.c
drivers/usb/host/xhci.h
This reverts commit 6732e1af29.
Replaced by commit 4e1813e52f ("exfat: fix memory leak in exfat_load_bitmap()").
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I323d80bccfc1c1fa021d9b86433a766f7bbebe5b
Some panel resolution is less than 2560 but pixel clock/fps is
relatively large, In this scene, VOP aclk need enter advance mode to
make sure VOP performance is enough. 4kp60 line duration is roughly
equal to 7500 ns, so we add a condition(linedur_ns < 7500) to enter
VOP aclk advance mode.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I50e15e8b05cfcf3c92704b8d96287099ce851686
Use flag CLK_MUX_ROUND_CLOSEST to be able to round the divider
to the closest one instead than roundup.
e.g. clk_set_rate 6150144 (6144000 * 1.001)
Before:
clk_get_rate - 6144000
After:
clk_get_rate - 6150145
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ic3d1ed3f4de0abf0c7e4c1027a68c2d2cb681029
This property is used to report the supported color format for each
resolution to userspace.
Change-Id: Ib2e8c712d7590b1cff77d03eb789bc49c18d6e74
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
The dolby core work at 1 pixel rate and the vop work at 2 pixel rate,
so the aclk_vop_doby : aclk_vop = 2 : 1 when enter dolby mode,
Non dovi mode clk tree:
aclk_vop_root 750000000
aclk_vop 750000000
aclk_vop_doby 750000000
aclk_vop_div2_src 375000000
Dovi mode clk tree:
aclk_vop_root 750000000
aclk_vop_doby 750000000
aclk_vop_div2_src 375000000
aclk_vop 375000000
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I649fd6263245a93c67a577262a95d23328880d06
The dolby vision will be supported by RK3588*-*V* SOCs,
e.g., RK3588S2-DV.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I1e8cf8f0e2b1521b858704df9a88261cec038ebb
DRM_MODE_BLEND_PIXEL_NONE usual be set at ARGB format and pixel alpha
is 0xff, no need to do blend, but vop2 platform at the following
scene, the cluster win1 and win0 do blend first, the blend result
with esmart do blend, we can't direct to close layer_mix0, because
the cluster win0 some area will do blend with esmart, so we keep
layer0 mix alpha be enabled and set as premutli mode.
zpos layer
2 cluster win1[ARGB/BLEND_COVERAGE] -->|
1 cluster win0[ARGB/BLEND_PIXEL_NONE]-->|cluster mix-->|
0 esmart[ARGB/BLEND_PIXEL_NONE] -->|layer0 mix
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I4ae75a9b443ea965527fd656821016acca35afe1
ROCKCHIP_DRM_CRTC_FEATURE_NEXT_HDR will be instead of by
ROCKCHIP_DRM_CRTC_FEATURE_DOVI,
VOP_FEATURE_NEXT_HDR will be instead of by VOP_FEATURE_DOVI.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ifae130599bc1a966ae316de002df3a1a3fec9d5a
We only need to ignore rk3588/rk3576 esmart pd turn on/off at
vop2_win_disable(), the following splice win reset should
be run.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I617f73786d93398965f5dcfac32f6fa76ee2e42e
This may be used by android solid color layer, userspace can set
plane BACKGROUND prop to assigned color, the plane will display
this color and no need to access DDR.
The color value should layout as following:
Enable:
val = BIT(31) | R << 16 | G << 8 | B;/* R/G/B can be 0 ~ 0xff */
For example, set a pure red color:
modetest -w 125:BACKGROUND:2164195328
Disable:
modetest -w 125:BACKGROUND:0
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ie1e077594e385e8ddd244f7c33b6182309a5c134
Guarantee the data is written before flexbus starts transmission.
Change-Id: I24e7e1b9e7f0fcd57b9269746251a05801007f3e
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Guarantee flexbus has completed transmission before reading.
Change-Id: I38d600a9feb1c0e586e70ec8cb581f803cf7902d
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
