[ Upstream commit 26d5bb9e4c ]
FMAN DMA read or writes under heavy traffic load may cause FMAN
internal resource leak; thus stopping further packet processing.
The FMAN internal queue can overflow when FMAN splits single
read or write transactions into multiple smaller transactions
such that more than 17 AXI transactions are in flight from FMAN
to interconnect. When the FMAN internal queue overflows, it can
stall further packet processing. The issue can occur with any one
of the following three conditions:
1. FMAN AXI transaction crosses 4K address boundary (Errata
A010022)
2. FMAN DMA address for an AXI transaction is not 16 byte
aligned, i.e. the last 4 bits of an address are non-zero
3. Scatter Gather (SG) frames have more than one SG buffer in
the SG list and any one of the buffers, except the last
buffer in the SG list has data size that is not a multiple
of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
With any one of the above three conditions present, there is
likelihood of stalled FMAN packet processing, especially under
stress with multiple ports injecting line-rate traffic.
To avoid situations that stall FMAN packet processing, all of the
above three conditions must be avoided; therefore, configure the
system with the following rules:
1. Frame buffers must not span a 4KB address boundary, unless
the frame start address is 256 byte aligned
2. All FMAN DMA start addresses (for example, BMAN buffer
address, FD[address] + FD[offset]) are 16B aligned
3. SG table and buffer addresses are 16B aligned and the size
of SG buffers are multiple of 16 bytes, except for the last
SG buffer that can be of any size.
Additional workaround notes:
- Address alignment of 64 bytes is recommended for maximally
efficient system bus transactions (although 16 byte alignment is
sufficient to avoid the stall condition)
- To support frame sizes that are larger than 4K bytes, there are
two options:
1. Large single buffer frames that span a 4KB page boundary can
be converted into SG frames to avoid transaction splits at
the 4KB boundary,
2. Align the large single buffer to 256B address boundaries,
ensure that the frame address plus offset is 256B aligned.
- If software generated SG frames have buffers that are unaligned
and with random non-multiple of 16 byte lengths, before
transmitting such frames via FMAN, frames will need to be copied
into a new single buffer or multiple buffer SG frame that is
compliant with the three rules listed above.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
From: Olliver Schinagl <oliver@schinagl.nl>
This patch adds a bit-banging gpio PWM driver. It makes use of hrtimers,
to allow nano-second resolution, though it obviously strongly depends on
the switching speed of the gpio pins, hrtimer and system load.
Each pwm node can have 1 or more "pwm-gpio" entries, which will be
treated as pwm's as part of a pwm chip.
Change-Id: Idd42bf6d79f8ce52275a15965b02af470f28da7c
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
It has two main use cases:
1) Allow drivers to reset their hardware via a GPIO line in a standard fashion
as supplied by the reset framework.
This allows adhoc driver code requesting GPIOs etc to be replaced with a
single call to device_reset().
2) Allow hardware on discoverable busses to be rest via a GPIO line
without driver modifications.
Examples of the second use case include:
* SDIO wifi modules
* USB hub chips with a reset line
In this second use case the reset has to be done externally to the driver
managing the hardware since resetting the device from the driver's probe()
method will either do nothing (if the device needs to be reset before
ennumeration will work) or cause racy beahviour (when the device disappears
from the bus during probe()).
So, in addition to providing a gpio based reset controller implementation
it is also possible to reset devices at boot via a DT property or from
userspace on request via sysfs attributes.
Change-Id: I316f9e622d99cff7167b57e8fd5ff73a34dc2a81
Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
Signed-off-by: Kevin Kim <ckkim@hardkernel.com>
[ Upstream commit 0df82dcd55 ]
Fully compatible with mcp2515, the mcp25625 have integrated transceiver.
This patch add the mcp25625 to the device tree bindings documentation.
Signed-off-by: Sean Nyekjaer <sean@geanix.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
PD#SWPL-8013
Problem:
separate dts config from driver
Solution:
separate dts config from driver
Verify:
verify by u202
Change-Id: I4de45ec213b86d12cdd9296f80de62f4f2dc6713
Signed-off-by: GongWei Chen <gongwei.chen@amlogic.com>
PD#SWPL-5636
Problem:
the clock measurement in SoC is changed
Solution:
add clock measurement
Verify:
test passed on ptm
Change-Id: I2325e9c76e27498c258449624b01f0deff9f7684
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#SWPL-5636
Problem:
pcie and several clk81 clocks are newly added in tm2 SoC
Solution:
add pcie and several clk81 clocks
Verify:
test passed on ptm
Change-Id: I8456d7fa8ffb6438e99d3f1cddee4a3ba846b933
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#SWPL-5651
Problem:
tm2 has 2 extra pins than tl1, should use new param data
Solution:
add tm2 param data
Verify:
T962e2_ab319
Change-Id: I77aaaead7b10024cd5f12354ba6b47db74ba96f5
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
PD#SWPL-5656
Problem:
tm2 need a static data pinctrl file to depict pins
Solution:
add relative codes to support tm2
Verify:
T962E2_ab319
Change-Id: I55206f9b3df6390e8821fd777d329ddf05dd8386
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
PD#SWPL-5395
Problem:
sm1 support double-edge trigger, current code do not support.
Solution:
add relatvie bitmask to support this function.
Verify:
ptm & sm1_skt
Change-Id: I48ebc9b38db868f946c49b6fd5f98d427b2669df
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
PD# SWPL-4823
Problem:
1. After stack optimization, stack memory cannot be
mapped as dma buffers and thus causing crypto dma failed to
generate correct result.
2. crypto dma was not enabled on G12B
Solution:
1. Move key_iv buffer from stack to memory provided by kzalloc
2. Enable crypto dma on G12B
3. Replace module_param with debugfs
4. Replace pr_err with dev_err
Verify:
verified on G12B
Change-Id: I6de682e3d1fc141f8c6179c7d91f9b4bff165eae
Signed-off-by: Matthew Shyu <matthew.shyu@amlogic.com>
Signed-off-by: Mingyen Hung <mingyen.hung@amlogic.com>
PD#SWPL-3437
Problem:
the arm64 does not support tl1
Solution:
add arm64 support for tl1
Verify:
test pass on x301
Change-Id: I9531731650c7e8e962f681e357580d3dd0eb0137
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
PD#SWPL-1513
Problem:
ab update can not work on P
Solution:
add dtsi for ab update for P
Verify:
test pass in ampere
Change-Id: I6ff219170a16c0081fba7297110e8dfaadcff401
Signed-off-by: Xindong Xu <xindong.xu@amlogic.com>
[ Upstream commit 321cc359d8 ]
We need this new compatibility string as we experienced different behavior
for this 10/100Mbits/s macb interface on this particular SoC.
Backward compatibility is preserved as we keep the alternative strings.
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
PD#172587: watchdog: meson: add watchdog support for tl1
TL1's watchdog is same with G12A.
Change-Id: Iaa8c502e6a8889a33ed2875e7a16cca07873738a
Signed-off-by: Bo Yang <bo.yang@amlogic.com>
PD#172587: pwm: meson: add support for tl1
Add support for tl1.
Change-Id: I5db1be16765a8e2f2a07815e6d7d139eec4dcf16
Signed-off-by: bichao.zheng <bichao.zheng@amlogic.com>
PD#172286: this commit changes mainly for GVA
1) keypad: add pca9557 keypad driver for new mic board D607.
Change-Id: I0d9ec9626362b3d87d6c55e5c967bfa4486b1472
Signed-off-by: jinrong.liao <jinrong.liao@amlogic.com>
Signed-off-by: Victor Wan <victor.wan@amlogic.com>
Conflicts:
drivers/md/dm-bufio.c
drivers/media/dvb-core/dvb_frontend.c
drivers/usb/dwc3/core.c
drivers/usb/gadget/function/f_fs.c
[ Upstream commit 7e5d05e18b ]
We need to introduce a new compatible name for the Meson-AXG SoC
in order to support the RMII 100M ethernet PHY, since the PRG_ETH0
register of the dwmac glue layer is changed from previous old SoC.
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
[ Upstream commit 03d9fbc397 ]
The Meson8m2 SoC is a variant of Meson8 with some updates from Meson8b
(such as the Gigabit capable DesignWare MAC).
It is mostly pin compatible with Meson8, only 10 (existing) CBUS pins
get an additional function (four of these are Ethernet RXD2, RXD3, TXD2
and TXD3 which are required when the board uses an RGMII PHY).
The AOBUS pins seem to be identical on Meson8 and Meson8m2.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
PD#168480: reboot: meson: standardize the compatible property
Use 'amlogic,reboot' instead of 'aml,reboot'.
'aml,reboot' will be removed later.
Change-Id: I7d16795c98aa293fe204121ccd7da41c7d078f77
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Signed-off-by: Bo Yang <bo.yang@amlogic.com>
