commit 4881873f4c upstream.
According to the public S805 datasheet the RESET2 register uses the
following bits for the PIC_DC, PSC and NAND reset lines:
- PIC_DC is at bit 3 (meaning: RESET_VD_RMEM + 3)
- PSC is at bit 4 (meaning: RESET_VD_RMEM + 4)
- NAND is at bit 5 (meaning: RESET_VD_RMEM + 4)
Update the reset IDs of these three reset lines so they don't conflict
with PIC_DC and map to the actual hardware reset lines.
Fixes: 79795e20a1 ("dt-bindings: reset: Add bindings for the Meson SoC Reset Controller")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
PD#OTT-5603
Problem:
Configurate GPIO_AO 9 as mclk_0,it doesn't work.
Solution:
From SM1, the mclk pad register is changed.
Using standard clk tree to make it compitable.
Verify:
TM2, SM1.
Change-Id: I8d53296297536c90768495232570f33fc89db131
Signed-off-by: Shuai Li <shuai.li@amlogic.com>
PD#SWPL-7987
Problem:
TL1 DRM support
Solution:
add TL1 DRM support
Verify:
t962x2_x301
Change-Id: Ibc8ff641f42c0a416e80c3a420c1d808e0ad8b26
Signed-off-by: Dezhi Kong <dezhi.kong@amlogic.com>
PD#SWPL-8215
Problem:
1.clk81 can not switch to 24M
2.fixed pll can set rate
call clk_prepare_enable to open it
call clk_disable_unprepare to close it
Solution:
1.add clk81 mux clock
2.change fixed pll callback Read only to R/W
Verify:
test passed on tm2 ab301
Change-Id: I426d4307f19647afcb0166a23c1988df1b504807
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#SWPL-9646
Problem:
unsupport multi-layer
Solution:
add multi-layer support
Verify:
verify by w400 with modetest command
Change-Id: I5cd50761d2ab9cfff0f80d38e20455044c7a33fd
Signed-off-by: Dezhi Kong <dezhi.kong@amlogic.com>
PD#SWPL-8050
Problem:
current driver does not support rca ir protocol
Solution:
add register setting and code for rca use REMOTE_RYPE_RCA to configure.
Verify:
G12b_W400 & tl1 x301
Change-Id: I76d860d66a43071803fb60debeafcbf18f42b283
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
PD#SWPL-5636
Problem:
pcie and several clk81 clocks are newly added in tm2 SoC
Solution:
add pcie and several clk81 clocks
Verify:
test passed on ptm
Change-Id: I8456d7fa8ffb6438e99d3f1cddee4a3ba846b933
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#SWPL-5656
Problem:
tm2 need a static data pinctrl file to depict pins
Solution:
add relative codes to support tm2
Verify:
T962E2_ab319
Change-Id: I55206f9b3df6390e8821fd777d329ddf05dd8386
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
PD#SWPL-5407
Problem:
not include sm1 special defined clk
Solution:
add this clk
Verify:
sm1_skt
Change-Id: Iaf20aebe377d077d95eb053f7eea99473e3ac45d
Signed-off-by: Shunzhou Jiang <shunzhou.jiang@amlogic.com>
PD#SWPL-5555
Problem:
Current driver does not support both NEC and RC5
Solution:
Add a macro to depecit both NEC and RC5 state
Verify:
X301
Change-Id: I06894d033eabdb22db6e34fc2ad76e0390ef565f
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
PD#SWPL-3359
Problem:
the bt656 clocks were missing
Solution:
1.add bt656 clocks
2.fix several errors for media clocks
Verify:
test passed on u200
Change-Id: Iff69e790c78335930d6b2ea54f7544aca464e1fb
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#SWPL-3543
Problem:
current driver does not support toshiba ir remote control protocol
Solution:
add register setting and decode code for toshiba protocol
use REMOTE_TYPE_TOSHIBA/REMOTE_TYPE_NEC_TOSHIBA to configure toshiba
only/toshiba and nec.
Verify:
tl1_t962x2_x301
Change-Id: Idad70c3879fad6e8267f0c4d80d2447c34114103
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
PD#OTT-1025
Problem:
not support gen clock
Solution:
add gen clock
Verify:
test passed on g12a u200
Change-Id: I5199289d3cd1483fffbbd41f8d104369214ba302
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#172587: arm: dts: tl1: add initial device tree for tl1
Change-Id: I17734ee00d88a84ff19bf17f8edf519e3ed2f0e4
Signed-off-by: Bo Yang <bo.yang@amlogic.com>
PD#168480: pinctrl: txl: add pinctrl & gpio support for txl
Change-Id: I2496cdebfc283e90825f5dd7d20b0e16f57158d2
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Bo Yang <bo.yang@amlogic.com>
PD#168480: clk: txl: initial add clock driver
remove CLK_SET_RATE_PARENT flag for spicc.
If add CLK_SET_RATE_PARENT, it will change clk81 rate when set
spicc clock rate.
Change-Id: I80fec2c6d10611994ff40b06307e39b51ddb5a1a
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Signed-off-by: Bo Yang <bo.yang@amlogic.com>
PD#165090: add g12b.c for new clocks, include sys1_pll
Change-Id: If9234037eab5439cf1abfbcecc70c9f4eab6c954
Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
Signed-off-by: Hong Guo <hong.guo@amlogic.com>
Signed-off-by: Victor Wan <victor.wan@amlogic.com>
Conflicts:
arch/arm/configs/bcm2835_defconfig
arch/arm/configs/sunxi_defconfig
include/linux/cpufreq.h
init/main.c
PD#163124: pinctrl: keep the same GPIO ID after adding GPIOV_0 for G12A
Change-Id: I45b99df3a15e2bf0f7ad34ae8705dc4a509c70a1
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
PD#162992: pinctrl: add virtual GPIO "GPIOV_0" for g12a
The gpio is used to set the bit PERIPHS_PIN_MUX_2 BIT[17]. Please refer
the following method to use it.
1). set the PERIPHS_PIN_MUX_2 BIT[17] to <1>
mux_en {
groups = "sdio_dummy";
function = "sdio";
}
2). set the PERIPHS_PIN_MUX_2 BIT[17] to <0>
mux_dis {
groups = "GPIOV_0";
function = "gpio_periphs";
}
Change-Id: Ied0e6c71ed1ff8ab9a26cb76ec1508d83a4453d7
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
PD#161621: gpio: core: Decouple open drain/source flag with active low/high
Currently, the GPIO interface is said to Open Drain if it is Single
Ended and active LOW. Similarly, it is said as Open Source if it is
Single Ended and active HIGH.
The active HIGH/LOW is used in the interface for setting the pin
state to HIGH or LOW when enabling/disabling the interface.
In Open Drain interface, pin is set to HIGH by putting pin in
high impedance and LOW by driving to the LOW.
In Open Source interface, pin is set to HIGH by driving pin to
HIGH and set to LOW by putting pin in high impedance.
With above, the Open Drain/Source is unrelated to the active LOW/HIGH
in interface. There is interface where the enable/disable of interface
is ether active LOW or HIGH but it is Open Drain type.
Hence decouple the Open Drain with Single Ended + Active LOW and
Open Source with Single Ended + Active HIGH.
Adding different flag for the Open Drain/Open Source which is valid
only when Single ended flag is enabled.
Note: the patch from v4.14-rc6 with original commit ID 4c0facddb
Change-Id: I2f652614d3783caee3f510dc70e5e185379f49a7
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
PD#158433: arm64: dts: add i2c alias in aliases node
add alias for i2c controller to fasten i2c dev id
Change-Id: I87c1999766c69e9df63f551f0559b8028844d660
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#156734: pinctrl: add pinctrl&gpio support for g12a
the new pin feature (drive-strength) is first introduced in Meson
Series SoC [G12A]. we can refer the following example to use:
mux {
groups = "uart_ao_tx_a", "uart_ao_rx_a";
function = "uart_ao_a";
drive-strength = <1>;
}
the value of drive-strength can be set to 0/1/2/3, the larger
the value, the faster the slew rate.
Change-Id: I22c6967aa1d5de1b3f6acb84cb18a79b05c0403b
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
PD#156734: base clock tree for G12A,
include clk81, ee gate, sdemmc clock, fix/hifi/syspll/pcie plls, mpll, clkmsr
Change-Id: I9fe7c1d64d9db5d384070f5dcefdc69f5f60dbd2
Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
