Files
linux/drivers
David Wu a19f9979e4 ethernet: stmmac: rockchip: Fix the correct clock for mdc divider
The MDC clock is divider from APB Clock for rockchip's socs, if it
was from mac_clk, the mdc clk range might not be between the frequency
range 1.0 MHz - 2.5 MHz.

Change-Id: I4e4fcb1be239a8d78a39fc1f4e2af5bb87258798
Signed-off-by: David Wu <david.wu@rock-chips.com>
2021-08-06 09:11:42 +08:00
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