Yu-ting Shen cab5dec425 drm/amd/display: limit display clock to 100MHz to avoid FIFO error
[Why]
when changing display clock, SMU need to use power up DFS and use
DENTIST to ramp DFS DID to switch target frequency before switching back
to bypass.

[How]
fixed the minimum display clock to 100MHz, it's W/A the same with PCO.

Signed-off-by: Yu-ting Shen <Yu-ting.Shen@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25 11:10:08 -05:00
2020-01-20 11:42:57 +10:00
2019-12-09 10:36:44 -08:00
2020-01-20 11:42:57 +10:00
2020-01-20 11:42:57 +10:00
2020-01-11 14:33:39 -08:00
2019-10-29 04:43:29 -06:00
2020-01-20 11:42:57 +10:00
2020-01-19 16:02:49 -08:00

Linux kernel
============

There are several guides for kernel developers and users. These guides can
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In order to build the documentation, use ``make htmldocs`` or
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    https://www.kernel.org/doc/html/latest/

There are various text files in the Documentation/ subdirectory,
several of them using the Restructured Text markup notation.

Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
the problems which may result by upgrading your kernel.
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