Files
linux/include
Zheng Yang f8fbbc4520 drm: bridge: dw-hdmi: introduce mpll_cfg_420
RK3368/RK3399 mpll input clock rate is twice of mpll output
in YCBCR420 mode. This patch introduce mpll_cfg_420 to get
the platform YCBCR420 phy setting. If mpll_cfg_420 is not
exist, use mpll_cfg.

Change-Id: I7910a75394cf371a8008f8a83e3ab9ec14e9a68a
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
2017-12-11 15:27:58 +08:00
..
2017-10-05 09:41:48 +02:00