PD#SWPL-133117
Problem:
1 adapts to the new driver
2 some clock descriptions are incorrect
3 unified clock naming Convention
Solution:
fixed
Verify:
s1a_bg209
Change-Id: I4a7296a81b4662978b9aab225bf615ef4ec8747e
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-120773
Problem:
clock tree bringup for s1a
Solution:
add support
Verify:
pxp
Change-Id: I21040ed89cbd969bf71c250ef97b55592e4a43cb
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-120910
Problem:
s1a need power domain.
Solution:
add power domain in kernel.
Verify:
pxp
Change-Id: Iffb97862c55034de94806a21aace59aab023526e
Signed-off-by: hongyu.chen1 <hongyu.chen1@amlogic.com>
PD#SWPL-130649
Problem:
there is no gp1 pll
Solution:
add gp1 support
Verify:
t3x
Change-Id: I47954709035c28e20079de481a960924e68d3629
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#SWPL-128494
Problem:
1 not support non-secure ops function for cpu_cyn_clk
2 When c1 describes the same frequency, the corresponding
defined frequency is different.
Solution:
1 add non-secure ops function for cpu_cyn_clk
2 unify frequency to 666666666Hz
Verify:
c1_ae400
Change-Id: Idec9a54d7010e18336be02fd488239dd7114986b
Signed-off-by: yiting.deng <yiting.deng@amlogic.com>
PD#SWPL-124230
Problem:
1 fclk50m is not added to clock tree;
2 dsp clk failed to set the frequency;
3 clkid incorrectly defined.
Solution:
fixed
Verify:
c1_ae400
Change-Id: Ieef2f603f72a6b0104b295b37c4a9ec448923d7c
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-121112
Problem:
clock tree bringup for c1
Solution:
support
Verify:
c1_ae400
Change-Id: Iaeacc52b6ac8266604614c2394d4a867e6edc203
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-125774
Problem:
there is no range driver on 32bit os
Solution:
support
Verify:
TXHD2 be319
Change-Id: Ie8e40ade1c577d62a5cb551a4b3b08dd9d6056ac
Signed-off-by: junyi.zhao <junyi.zhao@amlogic.com>
PD#SWPL-125774
Problem:
there is no dmux
Solution:
fix it
Verify:
TXHD2 be319
Signed-off-by: junyi.zhao <junyi.zhao@amlogic.com>
Change-Id: Idc946009ed96e9d718f191f2d6ec02b01a1e6894
PD#SWPL-118428
Problem:
there is no txhd2 clk driver
Solution:
need to support clk driver
Verify:
TXHD2 PXP
Change-Id: I15f13c03768185a36a6a0eb607ff3835eaacd5b0
Signed-off-by: junyi.zhao <junyi.zhao@amlogic.com>
PD#SWPL-118417
Problem:
need power domain support in kernel.
Solution:
add power domain.
Verify:
pxp
Change-Id: I004ec6bc1bbbea2ec5c901bce88cf73435885e80
Signed-off-by: hongyu.chen1 <hongyu.chen1@amlogic.com>
PD#SWPL-118802
Problem:
1 not support non-secure ops function for cpu_cyn_clk
2 When each chip describes the same frequency, the corresponding
defined frequency is different.
Solution:
1 add non-secure ops function for cpu_cyn_clk
2 unify frequency to 666666666Hz
Verify:
all about board
Change-Id: Ia9fe27291ead5a56ed737c6f6aea97fbcddfd44f
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#SWPL-117193
Problem:
t3x sys pll does not work well for dvfs
Solution:
add cpu and sys pll support
Verify:
t3x
Change-Id: Ia615b66b1ebd8c04b6d66679b73e6261615767f6
Signed-off-by: jian.hu <jian.hu@amlogic.com>
PD#SWPL-111601
Problem:
need to support t3x reset driver
Solution:
add reset dt-bindings and dts node for t3x
Verify:
t3x_pxp
Change-Id: Ib20cab11a5f12a642f086432eecf17ca41681e60
Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
PD#SWPL-111280
Problem:
need power domain in kernel.
Solution:
add power domain driver.
Verify:
mimic
Change-Id: I70cfe372d8f549632283d208f5c4418b81e9d572
Signed-off-by: hongyu.chen1 <hongyu.chen1@amlogic.com>
PD#SWPL-111222
Problem:
Need to support t3x pinctrl & gpio function
Solution:
Add t3x pinctrl driver data
Verify:
t3x_mimic
Change-Id: I65a12add5ef9a3a445a6ac6ae033ca9f84412025
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
PD#SWPL-113624
Problem:
keep the same sequence with the cpu_dyn clock's design
Solution:
add cpu_dyn clock ops
Verify:
t5w at301
Change-Id: I5bcd1480fb600fbef9ffcf997bc4f215c8ba4a0d
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#SWPL-113083
Problem:
12m and 24m clock are lost
Solution:
added
Verify:
w400/ac200
Change-Id: I9e206bd76eb2da91be5c145d0274146d9253fe71
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-110163
Problem:
part of the clock of g12b/sm1 is lost
Solution:
add clocks
Verify:
ac200
Change-Id: I5c021c862dc8913ad6295cb143b9400b11b97e63
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-107164
Problem:
1 sys_pll/sys1_pll does not support to 1512M
2 clkid is stored in multiple header files
Solution:
1 added frequency point support
2 clkid is placed under the same header file
Verify:
w400/ac200
Change-Id: I47d7f7c36b830285cfa4800ca0d90651629edb7e
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Liming Xue