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46 Commits

Author SHA1 Message Date
Chuan Liu 0377ab14a9 clk: s1a: lost sar_adc clock [1/1] 
PD#SWPL-133117

Problem:
lost sar_adc clock

Solution:
add

Verify:
s1a_bg209

Change-Id: Ie6d3f62cdecc64e113fed51e2c41f93a679aad67
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
 2023-08-15 10:37:49 +08:00
Chuan Liu b713a7059f clk: s1a: fix known issues [1/2] 
PD#SWPL-133117

Problem:
1 adapts to the new driver
2 some clock descriptions are incorrect
3 unified clock naming Convention

Solution:
fixed

Verify:
s1a_bg209

Change-Id: I4a7296a81b4662978b9aab225bf615ef4ec8747e
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
 2023-08-15 10:36:50 +08:00
Chuan Liu 43b35e9123 clk: s1a: clock tree bringup [1/2] 
PD#SWPL-120773

Problem:
clock tree bringup for s1a

Solution:
add support

Verify:
pxp

Change-Id: I21040ed89cbd969bf71c250ef97b55592e4a43cb
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
 2023-08-15 10:36:03 +08:00
Jian Hu a117903841 clk: t3x: add gp1 support [1/1] 
PD#SWPL-130649

Problem:
there is no gp1 pll

Solution:
add gp1 support

Verify:
t3x

Change-Id: I47954709035c28e20079de481a960924e68d3629
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
 2023-07-09 15:08:35 -07:00
yiting.deng 1439098f49 clk: adapt cpu_dyn_clk in c1 branch [1/1] 
PD#SWPL-128494

Problem:
1 not support non-secure ops function for cpu_cyn_clk
2 When c1 describes the same frequency, the corresponding
defined frequency is different.

Solution:
1 add non-secure ops function for cpu_cyn_clk
2 unify frequency to 666666666Hz

Verify:
c1_ae400

Change-Id: Idec9a54d7010e18336be02fd488239dd7114986b
Signed-off-by: yiting.deng <yiting.deng@amlogic.com>
 2023-07-07 14:33:12 +08:00
Chuan Liu b5a9102fa4 clk: c1: update clock tree [1/1] 
PD#SWPL-124230

Problem:
1 fclk50m is not added to clock tree;
2 dsp clk failed to set the frequency;
3 clkid incorrectly defined.

Solution:
fixed

Verify:
c1_ae400

Change-Id: Ieef2f603f72a6b0104b295b37c4a9ec448923d7c
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
 2023-07-07 14:28:26 +08:00
Chuan Liu e3d9857b0f clk: c1: clock tree bringup [1/1] 
PD#SWPL-121112

Problem:
clock tree bringup for c1

Solution:
support

Verify:
c1_ae400

Change-Id: Iaeacc52b6ac8266604614c2394d4a867e6edc203
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
 2023-07-07 12:49:28 +08:00
pengzhao.liu e2515b3c23 kernel: c1 kernel bringup [1/1] 
PD#SWPL-121076

Problem:
c1 kernel bringup

Solution:
c1 kernel bringup

Verify:
AE400-C308X

Change-Id: Ica758daab67c582a2647bb4ca1e7d9fa58d62e0c
Signed-off-by: pengzhao.liu <pengzhao.liu@amlogic.com>
 2023-07-07 12:45:20 +08:00
junyi.zhao 091fa0738d clk: support pll range driver on 32bit os [1/1] 
PD#SWPL-125774

Problem:
there is no range driver on 32bit os

Solution:
support

Verify:
TXHD2 be319

Change-Id: Ie8e40ade1c577d62a5cb551a4b3b08dd9d6056ac
Signed-off-by: junyi.zhao <junyi.zhao@amlogic.com>
 2023-06-30 03:15:07 -07:00
junyi.zhao 0a028a6b56 clk: fix vapb_1 register fail [1/1] 
PD#SWPL-130041

Problem:
vapb_1 clk is invalid

Solution:
fix it CLK_ID

Verify:
T3X BC302

Change-Id: I1b196cbfcebe57fa7ea3d6b5e26820d66d59636b
Signed-off-by: junyi.zhao <junyi.zhao@amlogic.com>
 2023-06-30 01:51:13 -07:00
junyi.zhao c69ea1ba48 clk: add dmux clk [1/1] 
PD#SWPL-125774

Problem:
there is no dmux

Solution:
fix it

Verify:
TXHD2 be319

Signed-off-by: junyi.zhao <junyi.zhao@amlogic.com>
Change-Id: Idc946009ed96e9d718f191f2d6ec02b01a1e6894
 2023-06-29 10:34:02 +08:00
Jian Hu ae557798a5 clk: add sys pll and cpu clk support [1/1] 
PD#SWPL-125774

Problem:
txhd2 bringup

Solution:
add sys pll and cpu clk support

Verify:
txhd2 be311

Change-Id: I6283d3c12729382b5e1c69c0de1d7c54ae4f20f1
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
 2023-06-29 10:34:02 +08:00
jiebing chen 440fb802d2 Audio: bringup txhd2 audio [1/1] 
PD#SWPL-124883

Problem:
bringup txhd2 audio

Solution:
bringup txhd2 audio

Verify:
use txhd2

Change-Id: I63bcd61778cb7f89ad44bf01854d93d163c77630
Signed-off-by: jiebing chen <jiebing.chen@amlogic.com>
 2023-06-29 10:34:01 +08:00
junyi.zhao de73569ad7 clk: support txhd2 clk [1/1] 
PD#SWPL-118428

Problem:
there is no txhd2 clk driver

Solution:
need to support clk driver

Verify:
TXHD2 PXP

Change-Id: I15f13c03768185a36a6a0eb607ff3835eaacd5b0
Signed-off-by: junyi.zhao <junyi.zhao@amlogic.com>
 2023-06-29 10:33:57 +08:00
Chuan Liu 964c07ba87 clk: adapt cpu_dyn_clk [1/1] 
PD#SWPL-118802

Problem:
1 not support non-secure ops function for cpu_cyn_clk
2 When each chip describes the same frequency, the corresponding
defined frequency is different.

Solution:
1 add non-secure ops function for cpu_cyn_clk
2 unify frequency to 666666666Hz

Verify:
all about board

Change-Id: Ia9fe27291ead5a56ed737c6f6aea97fbcddfd44f
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
 2023-06-13 21:00:26 -07:00
jiebing chen 778b416c79 Audio: bring up t3x audio [1/1] 
PD#SWPL-117252

Problem:
bring up t3x audio

Solution:
bring up t3x audio

Verify:
use BC311

Change-Id: Ic8484ce63dad096a8c7d0a4631fae3f25b0e19df
Signed-off-by: jiebing chen <jiebing.chen@amlogic.com>
 2023-05-18 21:08:39 +08:00
jian.hu 883034ed3a clk: add vafe clock [1/1] 
PD#SWPL-117193

Problem:
vafe clock is missing

Solution:
add vafe clock

Verify:
t3x bc311

Change-Id: Id7494e44118392a7e21deddb94cc60e26d799f51
Signed-off-by: jian.hu <jian.hu@amlogic.com>
 2023-05-18 21:08:39 +08:00
jian.hu e28eb409e7 clk: add cpu and sys pll support [1/1] 
PD#SWPL-117193

Problem:
t3x sys pll does not work well for dvfs

Solution:
add cpu and sys pll support

Verify:
t3x

Change-Id: Ia615b66b1ebd8c04b6d66679b73e6261615767f6
Signed-off-by: jian.hu <jian.hu@amlogic.com>
 2023-05-18 21:08:39 +08:00
Jian Hu 1a08f478c2 clk: add t3x clk support [1/1] 
PD#SWPL-111593

Problem:
t3x clk bringup

Solution:
add t3x clk support

Verify:
t3x mimic

Change-Id: I97b83b7d53a8ad932685f7d5e606b75ccb73ed37
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
 2023-05-18 21:08:38 +08:00
Jian Hu 16946192ac dts: add t3x device tree [1/1] 
PD#SWPL-110944

Problem:
t3x bringup

Solution:
add t3x device tree

Verify:
t3x z1

Change-Id: I30365c1a1caafca531c2176070cb447b751d5a2f
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
 2023-05-18 21:08:38 +08:00
Jian Hu de435ac5d6 clk: add non-secure cpu_dyn clock ops [1/1] 
PD#SWPL-113624

Problem:
keep the same sequence with the cpu_dyn clock's design

Solution:
add cpu_dyn clock ops

Verify:
t5w at301

Change-Id: I5bcd1480fb600fbef9ffcf997bc4f215c8ba4a0d
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
 2023-04-27 06:52:22 +00:00
Jian Hu 8b11ef34f6 t5w: add basic dts and basic driver [1/1] 
PD#SWPL-113237

Problem:
t5w bringup

Solution:
1. add arm/arm64 dts
2. add clock driver
3. add gpio/pinctrl driver

Verify:
t5w at301

Change-Id: I04123e6de92f1ecd84bad81a68bc993fa73d2d2d
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
 2023-04-27 06:47:58 +00:00
tuan zhang d410418b0c bringup: Porting S5 on kernel5.15 [1/1] 
PD#SWPL-108694

Problem:
Porting S5 on kernel5.15.

Solution:
Porting S5 on kernel5.15.

Verify:
S928X-AX201

Change-Id: I0ef2bc47aa5d63752ffb70516c9fa19a8578af80
Signed-off-by: tuan zhang <tuan.zhang@amlogic.com>
 2023-04-15 08:55:56 +08:00
Chuan Liu c308b26ad6 g12b/sm1: add 24m/12m clock [1/1] 
PD#SWPL-113083

Problem:
12m and 24m clock are lost

Solution:
added

Verify:
w400/ac200

Change-Id: I9e206bd76eb2da91be5c145d0274146d9253fe71
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
 2023-04-04 19:48:16 +08:00
xing.fang 69871e4d8c Audio: G12B & SM1 Audio Bringup [1/1] 
PD#SWPL-104253

Problem:
G12B & SM1 Audio Bringup

Solution:
1) modify dts & dtsi
2) add audio clk driver for g12b
3) add audio pinctrl driver for g12b
4) add audio clk driver for sm1
5) fix PDM & Loopback clk issues for sm1

Verify:
local

Change-Id: Ic27720cc0a297610165fdb661931b00999422ab1
Signed-off-by: xing.fang <xing.fang@amlogic.com>
 2023-04-04 19:48:15 +08:00
Chuan Liu a608f917f3 g12b/sm1: add some lost clocks [1/1] 
PD#SWPL-110163

Problem:
part of the clock of g12b/sm1 is lost

Solution:
add clocks

Verify:
ac200

Change-Id: I5c021c862dc8913ad6295cb143b9400b11b97e63
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
 2023-04-04 19:37:02 +08:00
Chuan Liu 6a4094dcf6 g12a/g12b/sm1: update clock tree [1/1] 
PD#SWPL-107164

Problem:
1 sys_pll/sys1_pll does not support to 1512M
2 clkid is stored in multiple header files

Solution:
1 added frequency point support
2 clkid is placed under the same header file

Verify:
w400/ac200

Change-Id: I47d7f7c36b830285cfa4800ca0d90651629edb7e
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
 2023-04-04 19:35:44 +08:00
Chuan Liu 51c61d4047 g12b/sm1: add clock tree [1/1] 
PD#SWPL-104283

Problem:
porting to kernel5.15

Solution:
fixed

Verify:
w400/ac200

Change-Id: I858a7ffd12d64dcc8e1e8082977814de070052d0
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
 2023-04-04 19:35:44 +08:00
yao zhang1 d133d2ef28 bringup: Add dts and dtsi for g12b & sm1. [1/1] 
PD#SWPL-104242

Problem:
Bringup g12b & sm1

Solution:
Add dts and dtsi for g12b & sm1.

Verify:
g12b & sm1

Change-Id: Ic80ce592cb8d63fa903319a9689ea65cebe0a330
Signed-off-by: yao zhang1 <yao.zhang1@amlogic.com>
 2023-04-04 19:35:43 +08:00
qing.zhang be0fdd6a1a Audio: T3 Kernel 5.15 Bring up [1/1] 
PD#SWPL-97929

Problem:
codec no output

Solution:
add codec config

Verify:
T3

Change-Id: I3fb129fd393900b85328508f7a1b0cd260e3b481
Signed-off-by: qing.zhang <qing.zhang@amlogic.com>
 2022-12-02 14:04:55 +08:00
Jian Hu bc1e2176df clk: t5m: add clock support [1/1] 
PD#SWPL-96527

Problem:
there is no t5m clock driver

Solution:
add t5m clock driver

Verify:
t5m pxp

Change-Id: Id361e5085331737358f25d63cdcdb11195378e61
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
 2022-12-02 14:04:53 +08:00
jian zhou ee868eba9e audio: Android T Bringup - Audio [1/1] 
PD#SWPL-94119

Problem:
Android T Bringup - Audio

Solution:
1. add extn
2. add earc
3. add latest code from 5.4

Verify:
T7C

Change-Id: I4812f2fb07ee8990a76e56f3837e7d774d202c42
Signed-off-by: jian zhou <jian.zhou@amlogic.com>
 2022-11-08 22:29:23 -07:00
Wanwei Jiang e2ed346ed5 t7: bring up to console [1/1] 
PD#SWPL-93318

Problem:
bring up to console

Solution:
1. copy dts related files from kernel 5.4
2. modify the file style to meet the submission requirements
3. porting clock driver
4. porting pinctrl driver
5. modify secmon dts
6. modify the reg of aucpu in dts to solve kernel panic

Verify:
t7

Change-Id: Ia3b8b4e2bccbbccd3ab513f7dd2295d30aa91c24
Signed-off-by: Wanwei Jiang <wanwei.jiang@amlogic.com>
 2022-09-07 20:13:52 +08:00
Wanwei Jiang 3d65944517 t3: bring up to console [1/1] 
PD#SWPL-93002

Problem:
bring up to console

Solution:
1. copy dts related files from kernel 5.4
2. modify the file style to meet the submission requirements
3. modify the CPU register to solve the problem of stuck cpuidle
4. porting clk driver
5. porting pinctrl driver
6. modify the reg of aucpu in dts to solve kernel panic
7. modify secmon dts to solve serror kernel panic

Verify:
t3

Change-Id: Idf318911e58fdb059bbae1035d390021326870c2
Signed-off-by: Wanwei Jiang <wanwei.jiang@amlogic.com>
 2022-09-07 20:06:44 +08:00
Chuan Liu c4ca15f33b c3: some clock parent definitions are incorrect [1/1] 
PD#SWPL-91333

Problem:
1 vc9000e and hcodec of clock parent definitions are incorrect
2 clock name logic error occurs under clk_debug

Solution:
1 modify clock of parents
2 correct the logic

Verify:
aw419-c308l

Change-Id: Iaa4cc43d0a40d44f223fb6b059bc8da97e6d9d9f
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
 2022-08-28 22:48:00 -07:00
xing.fang 9ca835f632 Audio: c3 audio driver bringup [1/1] 
PD#SWPL-83869

Problem:
porting resample & vad function

Solution:
1) modify dts/dtsi for resample & vad
2) modify clock driver files for resample
3) remove the resampleA & reset from dtsi

Verify:
AW419_C308L

Signed-off-by: xing.fang <xing.fang@amlogic.com>
Change-Id: I47224ccd3293164df3a3eb115e43fd6e43ba7c00
 2022-07-11 04:14:25 -07:00
xing.fang abfb65a26a Audio: c3 audio bringup [1/1] 
PD#SWPL-83864

Problem:
Audio bringup for c3

Solution:
Audio bringup for c3

Verify:
AW419-C308L

Signed-off-by: xing.fang <xing.fang@amlogic.com>
Change-Id: I56caf86b30675ac59ebed47faed0e2da1995f089
 2022-06-30 18:20:41 +08:00
Chuan Liu 0b0a65ae90 c3: mclk_pll is undefined [1/1] 
PD#SWPL-84541

Problem:
1 mclk_pll is undefined
2 gp0/1_pll support 1152M
3 sys_clk and axi_clk define error

Solution:
1 add mclk_pll code
2 add gp0/1_pll config table
3 modify sys_clk and axi_clk define

Verify:
AW419-C308L

Change-Id: I3511cbdf596d43f2e269115f6bd4510fc4f6bd30
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
 2022-06-30 18:20:41 +08:00
Chuan Liu 0d479df10f c3: update clk tree code [2/2] 
PD#SWPL-83827

Problem:
1 add clk_notifier
2 pll clock register is incorrectly configured
3 pwm clk source of pwm defined error

Solution:
1 update clk tree code
2 optimize pll timing(https://scgit.amlogic.com/#/c/231673/)

Verify:
AW419-C308L

Change-Id: I7e2f1cc9143b37a493bfaba3163f1a173c164935
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
 2022-06-30 18:09:28 +08:00
Yu Tu 1074bb057e clk: sc2: add sc2 clktree driver [1/1] 
PD#SWPL-83300

Problem:
no sc2 clktree driver

Solution:
add sc2 clktree driver

Verify:
sc2_ah212

Signed-off-by: Yu Tu <yu.tu@amlogic.com>
Change-Id: I952b347791abb42af87ab2dc5c72b89ce5f6e76a
 2022-06-06 00:53:06 -07:00
qinglin.li 5f0e9ae872 dts: bring up sc2 dts [1/1] 
PD#SWPL-82995

Problem:
bring up sc2 dts

Solution:
bring up sc2 dts

Verify:
sc2-ah212

Signed-off-by: qinglin.li <qinglin.li@amlogic.com>
Change-Id: I83d7bb3df417ca620b128ea8ac598af05792b89d
 2022-05-27 02:16:33 -07:00
wanwei.jiang 310a61615c a1: aarch64 bring up to console [1/1] 
PD#SWPL-77520

Problem:
aarch64 bring up to console

Solution:
aarch64 bring up to console

Verify:
a1 ad409

Change-Id: I8d75dfa555e488548c1ad2aed0c4915279cb91a1
Signed-off-by: wanwei.jiang <wanwei.jiang@amlogic.com>
 2022-04-14 22:29:19 +08:00
Shunzhou Jiang 1f6f790fd0 c3: add c3 clock tree [1/1] 
PD#SWPL-74257

Problem:
add c3 clock tree

Solution:
add c3 clock tree

Verify:
pxp

Change-Id: I21b7921097ffb5bd91e3fad8f6a504b8912f13a5
Signed-off-by: Shunzhou Jiang <shunzhou.jiang@amlogic.com>
 2022-03-20 04:29:24 -07:00
wanwei.jiang daefdc103d audio: porting audio driver [1/1] 
PD#SWPL-72014

Problem:
porting audio driver from kernel5.10

Solution:
porting audio driver from kernel5.10

Verify:
s4d and C2 AF400

Signed-off-by: wanwei.jiang <wanwei.jiang@amlogic.com>
Change-Id: Ie69c274441619925df30ec20f85ae2b36e74bc6e
 2022-03-04 11:13:37 +08:00
wanwei.jiang 771f1ddc3b dts: porting c2 dts [1/1] 
PD#SWPL-70779

Problem:
porting c2 dts

Solution:
porting c2 dts

Verify:
C2 Af400

Change-Id: I1f34649a66fcecac7749d26aaa3d3a962fb743b9
Signed-off-by: wanwei.jiang <wanwei.jiang@amlogic.com>
 2022-01-19 18:34:58 +08:00
wanwei.jiang cae421a694 dts: init the dts of s4d_s905y4_ap222_drm [1/1] 
PD#SWPL-64323

Problem:
init the dts of s4d_s905y4_ap222_drm

Solution:
init the dts of s4d_s905y4_ap222_drm

Verify:
Build pass

Change-Id: I688f39d9993658a3f1191dbbe309cc5ff1f8a07e
Signed-off-by: wanwei.jiang <wanwei.jiang@amlogic.com>
 2021-11-16 15:13:15 +08:00