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drm/rockchip: dsi: make timing and lane rate more accurate

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use actual pixel or dot clock in the hardware to calc the
timings and lane rate if dclk can not be applied accurately.

Change-Id: I6c0bcaca35cb945a58cc50005b23c6c772c9a082
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
This commit is contained in:
Guochun Huang
2020-11-18 09:10:10 +08:00
committed by Tao Huang
parent afba90dde0
commit 09f5dd4822
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/drm/rockchip/dw-mipi-dsi.c
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@@ -981,7 +981,7 @@ static void dw_mipi_dsi_set_vid_mode(struct dw_mipi_dsi *dsi)
{
struct drm_display_mode *mode = &dsi->mode;
unsigned int lanebyteclk = (dsi->lane_mbps * USEC_PER_MSEC) >> 3;
unsigned int dpipclk = mode->clock;
unsigned int dpipclk = mode->crtc_clock;
u32 hline, hsa, hbp, hline_time, hsa_time, hbp_time;
u32 vactive, vsa, vfp, vbp;
u32 val;
@@ -1118,7 +1118,7 @@ static unsigned long dw_mipi_dsi_get_lane_rate(struct dw_mipi_dsi *dsi)
bpp = 24;
lanes = dsi->slave ? dsi->lanes * 2 : dsi->lanes;
tmp = (u64)mode->clock * 1000 * bpp;
tmp = (u64)mode->crtc_clock * 1000 * bpp;
do_div(tmp, lanes);
/* take 1 / 0.9, since mbps must big than bandwidth of RGB */